Shift register circuit

Patent metadata

Field	Value
Publication number	US-9490809-B2
Application number	US-201414277918-A
Country	US
Kind code	B2
Filing date	May 15, 2014
Priority date	Apr 7, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A shift register circuit includes a pull-down circuit, pull-down control circuit, a driving unit, a primary pull-down circuit and a gate driver circuit. The pull-down control circuit is electrically connected to the pull-down circuit and configured to provide an nth-stage pull-down control signal to the pull-down circuit. The a driving unit is electrically connected to the pull-down control circuit and configured to drive the pull-down control circuit. The primary pull-down circuit is electrically connected to the pull-down circuit. The gate driver circuit is electrically connected to the pull-down circuit and configured to output an nth-stage gate driving signal according to an nth-stage control signal. The driving unit is configured to receive a plurality of high-frequency clock signals and accordingly to pre-enable the pull-down control circuit, and n is a positive integer.

First claim

What is claimed is:

1. A shift register circuit, comprising:
a pull-down circuit;
a pull-down control circuit, electrically connected to the pull-down circuit and configured to enabled the pull-down circuit and provide an nth-stage pull-down control signal to the pull-down circuit;
a driving unit, electrically connected to the pull-down control circuit and configured to drive the pull-down control circuit;
a primary pull-down circuit, electrically connected to the pull-down circuit; and
a gate driver circuit, electrically connected to the pull-down circuit and configured to output an nth-stage gate driving signal according to an nth-stage control signal, wherein the driving unit is configured to receive a plurality of high-frequency clock signals and accordingly to pre-enable the pull-down control circuit in the overlaying period of the each two adjacent high-frequency clock signals, and n is a positive integer;
wherein the pull-down control circuit comprises:
a first transistor;
a second transistor, configured to have its gate terminal electrically connected to a second terminal of the first transistor, its first terminal electrically connected to a first terminal of the first transistor, and its second terminal electrically connected to the pull-down circuit and for providing the nth-stage pull-down control signal;
a third transistor, configured to have its gate terminal for receiving the nth-stage control signal, its first terminal electrically connected to the second terminal of the second transistor and the pull-down circuit, and its second terminal for receiving a low power supply voltage; and
a fourth transistor, configured to have its gate terminal for receiving the nth-stage control signal, its first terminal electrically connected to the second terminal of the first transistor and the gate terminal of the second transistor, and its second terminal for receiving the low power supply voltage.

2. The shift register circuit according to claim 1 , wherein the plurality of high-frequency clock signals comprise a (n−1)th-stage high-frequency clock signal, a nth-stage high-frequency clock signal and a (n+2)th-stage high-frequency clock signal, wherein the (n−1)th-stage high-frequency clock signal has a preset time lead relative to the nth-stage high-frequency clock signal, wherein enabled periods of the (n−1)th-stage high-frequency clock signal, the nth-stage high-frequency clock signal and the (n+2)th-stage high-frequency clock signal have a same time length.

3. The shift register circuit according to claim 2 , wherein the driving unit comprises:
a fifth transistor, configured to have its gate terminal and its first terminal electrically connected to each other, and its second terminal electrically connected to the gate terminal of the first transistor, the first terminal of the first transistor and the first terminal of the second transistor, wherein the fifth transistor is for receiving the (n−1)th-stage high-frequency clock signal to enable the pull-down control circuit;
a sixth transistor, configured to have its gate terminal and its first terminal electrically connected to each other, and its second terminal electrically connected to the gate terminal of the first transistor, the first terminal of the first transistor, the first terminal of the second transistor and the second terminal of the fifth transistor, wherein the sixth transistor is for receiving the nth-stage high-frequency clock signal to enable the pull-down control circuit; and
a seventh transistor, configured to have its gate terminal for receiving the (n+2)th-stage high-frequency clock signal, its first terminal electrically connected to the gate terminal of the first transistor, the first terminal of the first transistor, the second terminal of the fifth transistor and the second terminal of the sixth transistor, and its second terminal for receiving the low power supply voltage, wherein the seventh transistor is for stabilizing the pull-down control circuit in a low-voltage state.

4. The shift register circuit according to claim 3 , wherein the pull-down circuit comprises:
a twelfth transistor, configured to have its gate terminal electrically connected to the second terminal of the second transistor and the first terminal of the third transistor and for receiving the nth-stage pull-down control signal, its first terminal for receiving the nth-stage control signal, and its second terminal for receiving the nth-stage gate driving signal; and
a thirteenth transistor, configured to have its gate terminal electrically connected to the second terminal of the second transistor and the first terminal of the third transistor and for receiving the nth-stage pull-down control signal, its first terminal for receiving the nth-stage gate driving signal, and its second terminal for receiving the low supply voltage.

5. The shift register circuit according to claim 4 , further comprising a pull-up control circuit, the pull-up control circuit comprising:
a fourteenth transistor, configured to have its gate terminal for receiving the nth-stage control signal, and its first terminal for receiving the nth-stage high-frequency clock signal; and
a fifteenth transistor, configured to have its gate terminal electrically connected to a second terminal of the fourteen transistor, its first terminal electrically connected to the first terminal of the thirteenth transistor, and its second terminal for outputting a (n+2)th-stage control signal.

6. The shift register circuit according to claim 5 , wherein the primary pull-down circuit comprises:
a sixteenth transistor, configured to have its gate terminal for receiving a (n+4)th-stage gate driving signal, its first terminal for receiving a nth-stage control signal, and its second terminal for receiving the low supply voltage.

7. The shift register circuit according to claim 6 , wherein the gate driver circuit comprises:
a seventeenth transistor, configured to have its gate terminal for receiving the nth-stage control signal, its first terminal for receiving the nth-stage high-frequency clock signal, and its second terminal electrically connected to the first terminal of the thirteenth transistor and the first terminal of the fifteenth transistor and for outputting the nth-stage gate driving signal.

8. The shift register circuit according to claim 1 , wherein the plurality of high-frequency clock signals comprise a (n−2)th-stage high-frequency clock signal, a (n−1)th-stage high-frequency clock signal, a nth-stage high-frequency clock signal and a (n+3)th-stage high-frequency clock signal, wherein the (n−2)th-stage high-frequency clock signal has a preset time lead relative to the (n−1)th-stage high-frequency clock signal, the (n−1)th-stage high-frequency clock signal has the preset time lead relative to the nth-stage high-frequency clock signal, wherein enabled periods of the (n−2)th-stage high-frequency clock signal, the (n−1)th-stage high-frequency clock signal, the nth-stage high-frequency clock signal and the (n+3)th-stage high-frequency clock signal have a same time length.

9. The shift register circuit according to claim 8 , wherein the driving unit comprises:
an eighth transistor, configured to have its gate terminal and its first terminal electrically connected to each other and for receiving the (n−2)th-stage high-frequency clock signal;
a ninth transistor, configured to have its gate terminal electrically connected to the second terminal of the eighth transistor, its first terminal for receiving the (n−1)th-stage high-frequency clock signal, and its second terminal electrically connected to the gate terminal of the first transistor, the first terminal of the first transistor and the first terminal of the second transis

Assignees

• Au Optronics Corp

Inventors

• Lin Wei-Li
• Tung Che-Wei
• Chen Chia-Heng

Classifications

• H03K19/00384 Primary

  in field effect transistor circuits · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title