Programmable synchronous clock divider

Patent metadata

Field	Value
Publication number	US-9490777-B2
Application number	US-201514617950-A
Country	US
Kind code	B2
Filing date	Feb 10, 2015
Priority date	Feb 10, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.

First claim

The invention claimed is:

1. A clock divider for generating a divided clock signal, comprising:
a first logic unit for generating a compare value based on a divide value and at least one duty cycle input of an input clock;
a second logic unit for generating a first signal based on a comparison of the compare value and a count value;
a third logic unit for generating a second signal based on a comparison of the compare value, the count value, and a synchronization signal; and
a first multiplexer for generating the divided clock signal based on the first signal and the second signal, wherein a duty cycle value of the divided clock signal varies in accordance with the compare value.

2. The clock divider of claim 1 , wherein the at least one duty cycle input comprises a duty cycle enable signal and a duty cycle select signal.

3. The clock divider of claim 1 , wherein the first logic unit comprises:
an AND gate;
a second mux that receives the at least one duty cycle input, wherein a value of the duty cycle input is selected using an output of the AND gate;
an adder connected to the second mux for incrementing an output thereof;
a first latch connected to the adder for receiving an output of the adder;
a third mux connected to the first latch for receiving an output of the latch and the divide value; and
a second latch that provides a select input to the third mux for enabling and disabling a variation in a duty cycle of the divided clock signal.

4. The clock divider of claim 1 , wherein the second logic unit comprises:
an adder for generating an intermediate compare value from the compare value;
a first comparator coupled to the adder for comparing the intermediate compare value and the count value; and
an AND gate connected to the first comparator for receiving a comparison result therefrom, and an input from a NAND gate, wherein the AND gate outputs the first signal.

5. The clock divider of claim 1 , wherein the third logic unit comprises:
an adder for generating an intermediate compare value from the compare value;
a comparator coupled to the adder for comparing the intermediate compare value and the count value;
an AND gate coupled to the comparator for receiving the comparison result, and to a NAND gate for receiving an input therefrom; and
an OR gate coupled to the AND gate for receiving an output thereof, and for receiving a synchronization signal, and generating the second signal.

6. The clock divider of claim 1 , further comprising:
a fourth logic unit for generating a ratio sample signal from the divide value, wherein an output of the fourth logic unit is coupled to the first logic unit for providing the ratio sample signal thereto.

7. The clock divider of claim 6 , wherein the fourth logic unit comprises an adder coupled to a latch, wherein the adder adds one to the divide value and the incremented value is stored in the latch.

8. The clock divider of claim 1 , further comprising:
a latch, coupled to the third logic unit, for generating a long pulse based on the second signal, wherein the long pulse is input to the first mux in lieu of the second signal.

9. A method for generating a divided clock signal from an input clock signal, the method comprising:
generating, by a first logic unit, a compare value based on a divide value and at least one duty cycle input for an input clock;
generating, by a second logic unit, a first signal based on a comparison of the compare value and a count value;
generating, by a third logic unit, a second signal based on a comparison of the compare value and the count value; and
generating, by a first multiplexer, the divided clock signal based on the first signal and the second signal.

10. The method of claim 9 , wherein generating the first signal comprises modifying a width of the first signal, thereby providing a variation in the duty cycle of the divided clock signal.

11. The method of claim 10 , wherein generating the second signal comprises modifying a width of the second signal, thereby providing a variation in the duty cycle of the divided clock signal.

12. The method of claim 11 , further comprising enabling and disabling variation in the duty cycle of the input clock.

13. An integrated circuit including a clock divider for generating a divided clock signal, comprising:
a clock signal selector that receives a scan clock signal and a functional clock signal and outputs an input clock signal based on a scan mode signal;
a first logic unit for generating a compare value based on a divide value and at least one duty cycle value of the input clock signal;
a second logic unit for generating a first signal based on a comparison of the compare value and a count value;
a third logic unit for generating a second signal based on a comparison of the compare value and the count value;
a first multiplexer that receives the first signal at a first data input terminal the second signal at a second data input terminal, and the input clock signal at a select terminal, and outputs the divided clock signal.

14. The integrated circuit of claim 13 , wherein the at least one duty cycle value comprises a duty cycle enable signal and a duty cycle select signal.

15. The integrated circuit of claim 14 , further comprising a first latch having a data input terminal connected to the third logic unit for receiving the second signal, and an output terminal connected to the second data terminal of the first mux, wherein the second signal is delayed by the first latch before being input to the first multiplexer.

16. The integrated circuit of claim 15 , wherein the first logic unit comprises:
an AND gate;
a second mux that receives the at least one duty cycle input, wherein a value of the duty cycle input is selected using an output of the AND gate;
an adder connected to the second mux for incrementing an output thereof;
a first latch connected to the adder for receiving an output of the adder;
a third mux connected to the first latch for receiving an output of the latch and the divide value; and
a second latch that provides a select input to the third mux for enabling and disabling a variation in a duty cycle of the divided clock signal.

17. The integrated circuit of claim 15 , wherein the second logic unit comprises:
an adder for generating an intermediate compare value from the compare value;
a first comparator coupled to the adder for comparing the count value and the intermediate compare value; and
an AND gate connected to the first comparator for receiving a comparison result therefrom, and an input from a NAND gate, wherein the AND gate outputs the first signal.

18. The integrated circuit of claim 15 , wherein the third logic unit comprises:
an adder for generating an intermediate compare value from the compare value;
an comparator coupled to the adder for comparing the count value and the intermediate compare value;
an AND gate coupled to the comparator for receiving the comparison result, and to a NAND gate for receiving an input therefrom; and
an OR gate coupled to the AND gate for receiving an output thereof, and for receiving a synchronization signal, and generating the second signal.

19. The integrated circuit of claim 15 , further comprising a fourth logic unit for generating a ratio sample signal from the divide value, wherein an output of the fourth logic unit is coupled to the first logic unit for providing the ratio sample signal thereto.

20. The integrated circuit of claim 10 , wherein the fourth logic unit comprises an adde

Assignees

• Ali Inayat
• Dodeja Puneet
• Jain Sachin
• Freescale Semiconductor Inc

Inventors

• Ali Inayat
• Dodeja Puneet
• Jain Sachin

Classifications

• H03K23/002

  using semiconductor devices (H03K23/78, H03K23/80, H03K23/84 take precedence) · CPC title

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K21/10

  comprising logic circuits · CPC title

• H03K23/00

  Pulse counters comprising counting chains; Frequency dividers comprising counting chains (H03K29/00 takes precedence) · CPC title

• H03K21/026

  comprising logic circuits · CPC title