Power amplifier

Patent metadata

Field	Value
Publication number	US-9490758-B2
Application number	US-201314379651-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	Dec 25, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

There is provided a power amplifier capable of readily reducing odd-order harmonic waves even in high frequencies. This power amplifier includes n current sources (where “n” is a natural number equal to or greater than 3) that cause predetermined currents to flow; n switches that open and close current paths of the n current sources, respectively; and a signal generating section that generates n timing signals for turning on/off the n switches, respectively. In the power amplifier, the n timing signals are signals that have an identical duty ratio and that are different in phase; and the power amplifier outputs a signal amplified in power based on the currents flowing through the n current sources.

First claim

The invention claimed is:

1. A power amplifier comprising:
n current sources (where “n” is a natural number equal to or greater than 3) that cause predetermined currents to flow;
n switches that open and close current paths of the n current sources, respectively; and
a signal generating section that generates n timing signals according to an input signal, said n timing signals having an identical duty ratio and being different in phase, for turning on/off the n switches, respectively, wherein:
the power amplifier outputs a signal amplified in power based on the currents flowing through the n current sources.

2. The power amplifier according to claim 1 , wherein the n current sources comprise:
a reference current source that causes a reference current to flow; and
n current mirror circuits that transfer the reference current.

3. The power amplifier according to claim 1 , wherein the n switches are n MOS transistors.

4. The power amplifier according to claim 1 , wherein the n is 3; and
the n timing signals are signals whose phases are shifted by 0, 45, and 90 degrees, respectively.

5. The power amplifier according to claim 1 , wherein
the n is 3; and
the n current sources have a current value ratio of 1:2 1/2 :1.

6. The power amplifier according to claim 3 , wherein the n MOS transistors that are the n switches have constant channel lengths L, and channel widths W having sizes proportional to current values of the corresponding n current sources, respectively.

7. A power amplifier comprising:
n current sources (where “n” is a natural number equal to or greater than 3) that cause predetermined currents to flow;
n switches that open and close current paths of the n current sources, respectively;
a signal generating section that generates n timing signals for turning on/off the n switches, respectively; and
one or more load adjustment MOS transistors that have a gate terminal coupled with a gate terminal of one or more MOS transistors having a smaller size than the other MOS transistors among the n MOS transistors, wherein:
the n timing signals are signals that have an identical duty ratio and that are different in phase;
the power amplifier outputs a signal amplified in power based on the currents flowing through the n current sources;
the n switches are n MOS transistors;
the n MOS transistors that are the n switches have constant channel lengths L, and channel widths W having sizes proportional to current values of the corresponding n current sources, respectively;
the one or more load adjustment MOS transistors have drains and sources connected in a way that does not allow the currents to flow between the drains and the sources; and
loads of the gate terminals of the n MOS transistors are made substantially equal to each other by addition of a gate load of the load adjustment MOS transistors.

8. A power amplifier comprising:
n current sources (where “n” is a natural number equal to or greater than 3) that cause predetermined currents to flow;
n switches that open and close current paths of the n current sources, respectively; and
a signal generating section that generates n timing signals for turning on/off the n switches, respectively, wherein:
the n timing signals are signals that have an identical duty ratio and that are different in phase;
the power amplifier outputs a signal amplified in power based on the currents flowing through the n current sources;
the n is an even number equal to or greater than 6;
half of the n current sources, the n switches, and the n timing signals is categorized as a first group, and the remaining half thereof is categorized as a second group,
the first group and the second group operate in opposite phases, and
the power amplifier outputs a signal amplified in power based on a difference between a total current flowing through n/2 current sources in the first group and a total current flowing through n/2 current sources in the second group.

9. The power amplifier according to claim 8 , wherein:
the n current sources include three current sources in a first group and three current sources in a second group;
the n switches include three switches in a first group corresponding to the three current sources in the first group and three switches in a second group corresponding to the three current sources in the second group; and
the n timing signals include three timing signals in a first group corresponding to the three switches in the first group and three timing signals in a second group corresponding to the three switches in the second group, wherein:
a ratio of current values of the three current sources in the first group is 1:2 1/2 :1;
a ratio of current values of the three current sources in the second group is 1:2 1/2 :1;
the three timing signals in the first group are signals whose phases are shifted by 0, 45, and 90 degrees, respectively;
the three timing signals in the second group are signals whose phases are shifted by 180, 225, and 270 degrees; and
the power amplifier outputs a signal amplified in power based on a difference between a total current flowing through the three current sources in the first group and a total current flowing through the three current sources in the second group.

10. A power amplifier comprising:
n current sources (where “n” is a natural number equal to or greater than 3) that cause predetermined currents to flow;
n switches that open and close current paths of the n current sources, respectively; and
a signal generating section that generates n timing signals for turning on/off the n switches, respectively;
harmonic-wave-reduction current sources that cause predetermined currents to flow;
harmonic-wave-reduction switches that open and close current paths of the harmonic-wave-reduction current sources; and
a signal generating section that generates a harmonic-wave-reduction timing signal for turning on/off the harmonic-wave-reduction switches, wherein:
the n timing signals are signals that have an identical duty ratio and that are different in phase;
the power amplifier outputs a signal amplified in power based on the currents flowing through the n current sources;
a frequency of the harmonic-wave-reduction timing signal is twice the frequency of the timing signals; and
currents of the harmonic-wave-reduction current sources are added to an output of the power amplifier.

11. The power amplifier according to claim 10 , wherein the phase of the harmonic-wave-reduction timing signal is set as a phase for reducing a harmonic wave included in the signal amplified in power.

12. The power amplifier according to claim 10 , further comprising a number switching section that selectively switches a number of current sources and a number of switches to be operated among the plurality of the harmonic-wave-reduction current sources and the plurality of the harmonic-wave-reduction switches.

Assignees

• Panasonic Corp

Inventors

• Okada Eiji

Classifications

• H03F2203/21184

  the supply current of a power amplifier being continuously measured, e.g. by a resistor, a current mirror, to produce a controlling signal · CPC title

• H03F2203/21136

  An input signal of a power amplifier being on/off switched · CPC title

• H03F3/2178

  using more than one switch or switching amplifier in parallel or in series (H03F3/2173, H03F3/2175 take precedence) · CPC title

• H03F3/211 Primary

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F2203/21109

  An input signal being distributed by switching to a plurality of paralleled power amplifiers · CPC title