Fully integrated thermoelectric devices and their application to aerospace de-icing systems

Patent metadata

Field	Value
Publication number	US-9490414-B2
Application number	US-201213602019-A
Country	US
Kind code	B2
Filing date	Aug 31, 2012
Priority date	Aug 31, 2011
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A thermoelectric module and methods for making and applying same provide an integrated, layered structure comprising first and second, thermally conductive, surface volumes, each in thermal communication with a separate respective first and second electrically conductive patterned trace layers, and an array of n-type and p-type semiconducting elements embedded in amorphous silica dielectric and electrically connected between the first and second patterned trace layers forming a thermoelectric circuit.

First claim

What is claimed is:

1. A microelectronic circuit module comprising:
a heat producing semiconductor chip mounted on a packaging element that has micro-channels through which a working fluid is passed to collect and transfer heat from the semiconductor chip;
a thermoelectric module comprising a network of micro-channels embedded within silica dielectric through which the heated working fluid is circulated; and
a first thermally isolated thermoelectric circuit embedded within silica dielectric that consists of a linear array of MAX-phase electrodes interleaved between alternating n-type and p-type semiconducting elements,
wherein the MAX-phase electrodes contain micro-channels through which the working fluid is circulated and progressively cooled.

2. The module of claim 1 , further comprising a set of thermally isolated secondary thermoelectric circuits embedded within the silica dielectric adjacent to the first thermoelectric circuit and consist of a n-type and p-type semiconducting elements configured in parallel between MAX-phase electrodes,
wherein a hot electrode of the secondary thermoelectric circuits contain micro-channels through which the working fluid is passed and cooled, and a cold electrode of the secondary thermoelectric circuits is in thermal communication with a thermal reservoir.

3. The module of claim 2 , further comprising a controller circuit that monitors the temperature of the various MAX-phase electrodes and adjusts the voltage drops across the different thermoelectric circuits used in the circuit.

4. The module of claim 1 , further comprising a MEMS pump adapted for circulating the working fluid.

5. The module of claim 1 , wherein the silica dielectric includes distributed added crystalline compounds arranged to improve thermal insulation over that of pure amorphous silica.

6. The module of claim 5 , wherein the crystalline compounds include skutterudite crystals separated by atomic layers of alkali ions.

7. The module of claim 1 , farther comprising first and second, thermally conductive, surface volumes, each in thermal communication with a separate respective first and second electrically conductive patterned trace layers and connected between the alternating n-type and p-type semiconducting elements.

8. The module of claim 7 , further comprising input and output ports providing external electrical connection to at least one of the first or second patterned trace layers.

9. The module of claim 7 , Wherein the first and second surface volumes comprise a MAX-phase materials.

10. The module of claim 9 , further comprising an insulating layer comprising an aluminum nitride MAX-phase material that electrically insulates the first and second surface volumes from their respective first and second patterned trace layers.

11. The module of claim 7 , wherein the first or second surface volume forms a leading edge of an air-flow surface.

12. The module of claim 1 , wherein the n-type and p-type semiconducting elements are formed from materials selected from the group consisting of: Skutterudites (AB3), complex Skutterudites (Z 2 A 8 B 13 ), elemental group IV semiconductor Si, Ge, alloyed group IV semiconductor consisting of Si, Ge, Sn, Bi, III-V compound semiconductor, II-VI compound semiconductor, IV-VI compound, metal oxide and mixed metal oxide semiconductor materials.

13. The module of claim 1 , wherein the semiconducting elements have carrier concentrations in the range of 10 17 to 10 19 carriers-cm −3 .

14. The module of claim 1 , further comprising ohmic contacts formed in the semiconducting elements having heavily doped layers in the range of 10 19 to 10 21 carriers-cm −3 , that electrically connect the semiconductor elements to the first and second patterned trace layers.

15. The module of claim 1 , wherein the semiconducting elements have a polycrystalline microstructure wherein the size of polycrystalline gains is less than 100 nm.

16. The module of claim 15 , wherein the polycrystalline grains form quantum dots comprising a semiconducting granular core with a chemically distinct grain boundary material.

Assignees

• De Rochemont L Pierre

Inventors

• De Rochemont L Pierre

Classifications

• B64D15/12 Primary

  by electric heating (heating arrangements specially adapted for transparent or reflecting areas H05B3/84) · CPC title

• H01L35/30

  Electricity · mapped topic

• H01L35/18

  Electricity · mapped topic

• H01L35/32 Primary

  Electricity · mapped topic

• H10N10/8556

  comprising compounds containing germanium or silicon · CPC title