Annealing for damage free laser processing for high efficiency solar cells
US-9214585-B2 · Dec 15, 2015 · US
US9490386B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9490386-B2 |
| Application number | US-201615041814-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 11, 2016 |
| Priority date | Dec 13, 2012 |
| Publication date | Nov 8, 2016 |
| Grant date | Nov 8, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A method of processing a semiconductor assembly is presented. The method includes fabricating a photovoltaic module including a semiconductor assembly. The fabrication step includes performing an efficiency enhancement treatment on the semiconductor assembly, wherein the efficiency enhancement treatment includes light soaking the semiconductor assembly, and heating the semiconductor assembly. The semiconductor assembly includes a window layer having an average thickness less than about 80 nanometers, wherein the window layer includes cadmium and sulfur. A related system is also presented.
Opening claim text (preview).
The invention claimed is: 1. A method, comprising: fabricating a photovoltaic module comprising a semiconductor assembly; wherein the fabrication step comprises performing an efficiency enhancement treatment on the semiconductor assembly; wherein the efficiency enhancement treatment comprises light soaking the semiconductor assembly, and heating the semiconductor assembly; wherein the efficiency enhancement treatment comprises an accelerated lifetime light-soaking treatment; wherein the semiconductor assembly comprises a window layer having an average thickness less than about 80 nanometers, and wherein the window layer comprises cadmium and sulfur. 2. The method of claim 1 , wherein the efficiency enhancement step comprises heating the semiconductor assembly at a temperature greater than 65° C. 3. The method of claim 1 , wherein the efficiency enhancement step comprises heating the semiconductor assembly at a temperature greater than 105° C. 4. The method of claim 1 , wherein the efficiency enhancement step comprises heating the semiconductor assembly at a temperature in a range from 105° C. to 200° C. 5. The method of claim 1 , wherein light soaking step comprises exposing the semiconductor assembly to a light intensity in a range from about 0.01 Sun to about 10 Sun. 6. The method of claim 1 , wherein the efficiency enhancement step comprises heating the semiconductor assembly for a time duration less than about 20 hours. 7. The method of claim 1 , wherein the efficiency enhancement step comprises heating the semiconductor assembly for a time duration less than about 10 hours. 8. The method of claim 1 , wherein the efficiency enhancement step comprises light soaking the semiconductor assembly under open-circuit conditions. 9. The method of claim 1 , wherein the fabrication step further comprises a step of forming the semiconductor assembly, the forming step comprising: disposing a transparent conductive layer on a first support; disposing the window layer on a transparent conductive layer; disposing an absorber layer on the window layer; and disposing a back contact layer on the absorber layer. 10. The method of claim 9 , wherein the efficiency enhancement step is effected simultaneously with, or after the step of disposing the back contact layer on the absorber layer. 11. The method of claim 9 , wherein the efficiency enhancement step is effected before the step of disposing the back contact layer on the absorber layer. 12. The method of claim 9 , wherein the fabrication step further comprises laminating a back substrate to the back contact layer, and wherein the energy enhancement step is effected simultaneously with, or after the lamination step. 13. The method of claim 9 , wherein the fabrication step further comprises laminating a back substrate to the back contact layer, and wherein the energy enhancement step is effected before the lamination step. 14. The method of claim 1 , wherein the steps of light soaking and heating the semiconductor assembly are effected simultaneously. 15. The method of claim 1 , wherein the window layer comprises cadmium sulfide, oxygenated cadmium sulfide, cadmium zinc sulfide, or combinations thereof. 16. The method of claim 1 , wherein the window layer has an average thickness less than about 60 nanometers. 17. The method of claim 1 , wherein the window layer comprises a discontinuous layer. 18. The method of claim 9 , wherein the absorber layer comprises cadmium telluride, cadmium zinc telluride, cadmium sulfur telluride, cadmium manganese telluride, cadmium magnesium telluride, or combinations thereof. 19. The method of claim 18 , wherein at least a portion of the absorber layer further comprises at least one element from Group IB. 20. A method, comprising: fabricating a photovoltaic module wherein the fabrication step comprises performing an efficiency enhancement treatment on a semiconductor assembly; wherein the efficiency enhancement treatment comprises light soaking the semiconductor assembly, and heating the semiconductor assembly; wherein the efficiency enhancement treatment comprises an accelerated lifetime light-soaking treatment; wherein the semiconductor assembly comprises an absorber layer, and wherein the absorber layer comprises cadmium and tellurium. 21. The method of claim 20 , wherein the semiconductor assembly comprises a plurality of layers disposed in a superstrate configuration. 22. The method of claim 20 , wherein the semiconductor assembly comprises a window layer, and wherein the window layer comprises cadmium and sulfur. 23. The method of claim 20 , wherein the semiconductor assembly comprises a window layer, and wherein the window layer comprises cadmium and selenium. 24. The method of claim 22 , wherein the window layer has an average thickness less than about 80 nanometers.
Solar cells from Group II-VI materials · CPC title
Cross-Sectional Technologies · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.