Capping dielectric structures for transistor gates

Patent metadata

Field	Value
Publication number	US-9490347-B2
Application number	US-201514925741-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Sep 30, 2011
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

The present description relates to the field of fabricating microelectronic transistors, including non-planar transistors, for microelectronic devices. Embodiments of the present description relate to the formation a recessed gate electrode capped by a substantially void-free dielectric capping dielectric structure which may be formed with a high density plasma process.

First claim

What is claimed is:

1. A method of fabricating a transistor gate, comprising:
forming a pair of gate spacers;
forming a gate electrode disposed between and contacting the pair of gate spacers;
removing a portion of the gate electrode to form a recess;
high density plasma depositing a capping dielectric structure within the recess on a top surface of the recessed gate electrode and between the pair of gate spacers;
forming a source/drain region;
forming at least one dielectric material over the source/drain region, the non-planar transistor gate spacers, and the capping dielectric structure; and
forming a contact opening through the at least one dielectric material to expose at least a portion of the source/drain region and which removes a portion of the capping dielectric structure.

2. The method of claim 1 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing a silicon nitride capping dielectric structure.

3. The method of claim 1 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing a silicon carbide capping dielectric structure.

4. The method of claim 1 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing the capping dielectric structure at a temperature between about 300° C. and 600° C.

5. A method comprising:
forming a non-planar transistor fin;
forming a pair of non-planar transistor gate spacers adjacent the sacrificial non-planar transistor fin;
depositing conductive gate material between and contacting the non-planar transistor gate spacers;
removing a portion of the conductive gate material to form a recess between the non-planar transistor gate spacers;
forming a capping dielectric structure within the recess by high density plasma depositing a dielectric material;
forming a source/drain region;
forming at least one dielectric material over the source/drain region, the non-planar transistor gate spacers, and the capping dielectric structure; and
forming a contact opening through the at least one dielectric material to expose at least a portion of the source/drain region and which removes a portion of the capping dielectric structure.

6. The method of claim 5 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing a silicon nitride capping dielectric structure.

7. The method of claim 5 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing a silicon carbide capping dielectric structure.

8. The method of claim 5 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing the capping dielectric structure at a temperature between about 300° C. and 600° C.

9. The method of claim 5 , further comprising forming a gate dielectric adjacent the non-planar transistor fin.

10. A method comprising:
forming a sacrificial non-planar transistor gate over a non-planar transistor fin;
depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor fin;
forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate;
forming a source/drain region;
removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin;
forming a gate dielectric adjacent the non-planar transistor fin within the gate trench;
depositing conductive gate material within the gate trench;
removing a portion of the conductive gate material to form a recess between the non-planar transistor gate spacers;
forming a capping dielectric structure within the recess by high density plasma depositing a dielectric material;
forming at least one dielectric material over the source/drain region, the non-planar transistor gate spacers, and the capping dielectric structure; and
forming a contact opening through the at least one dielectric material to expose at least a portion of the source/drain region and which removes a portion of the capping dielectric structure.

11. The method of claim 10 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing a silicon nitride capping dielectric structure.

12. The method of claim 10 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing a silicon carbide capping dielectric structure.

13. The method of claim 10 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing the capping dielectric structure at a temperature between about 300° C. and 600° C.

Assignees

• Intel Corp

Inventors

• Rosenbaum Aaron W
• Mei Din-How
• Pradhan Sameer S

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10D64/01354

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title