Methods of forming nanowire devices with doped extension regions and the resulting devices

Patent metadata

Field	Value
Publication number	US-9490340-B2
Application number	US-201414308138-A
Country	US
Kind code	B2
Filing date	Jun 18, 2014
Priority date	Jun 18, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.

First claim

What is claimed:

1. A method of forming a nanowire device, comprising:
forming a gate structure above a plurality of semiconductor material layers;
patterning said plurality of semiconductor material layers using said gate structure as a mask to expose first and second exposed end surfaces of each layer not covered by said gate structure;
forming doped extension regions in said first and second exposed end surfaces of said semiconductor material layers; and
after forming said doped extension regions, forming epi semiconductor material in source and drain regions of said nanowire device.

2. The method of claim 1 , further comprising recessing at least a first of said semiconductor material layers relative to a second of said semiconductor material layers before forming said doped extension regions.

3. The method of claim 1 , wherein forming said doped extension regions comprises forming said doped extension regions such that said semiconductor material layers have substantially the same dopant profile.

4. The method of claim 1 , wherein forming said epi semiconductor material comprises forming said epi semiconductor material such that it contacts said doped extension regions.

5. The method of claim 1 , wherein forming said doped extension regions comprises doping said first and second exposed end surfaces by performing a plasma doping process.

6. The method of claim 1 , wherein forming said doped extension regions comprises doping said first and second exposed end surfaces by performing an angled ion implantation process.

7. The method of claim 1 , further comprising:
removing said gate structure so as to define a gate cavity that exposes at least a portion of said patterned plurality of semiconductor material layers,
performing at least one etching process through said gate cavity so as to remove at least a first of said patterned plurality of semiconductor material layers selectively relative to at least a second of said patterned plurality of semiconductor material layers; and
forming a replacement gate structure in said gate cavity.

8. A method of forming a nanowire device, comprising:
forming a second sidewall spacer adjacent to a first sidewall spacer;
patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces;
removing said second sidewall spacer, thereby exposing at least a portion of said patterned semiconductor material layers;
recessing at least a first of said semiconductor material layers relative to a second of said semiconductor material layers;
removing said first sidewall spacer, thereby exposing at least another portion of said patterned semiconductor material layers; and
forming doped extension regions in at least said exposed portions of said patterned semiconductor material layers.

9. The method of claim 8 , wherein forming said doped extension regions comprises forming said doped extension regions such that said patterned semiconductor material layers have substantially the same dopant profile.

10. The method of claim 8 , further comprising forming a gate structure above said plurality of semiconductor material layers.

11. The method of claim 10 , further comprising forming said first sidewall spacer adjacent to said gate structure.

12. A method of forming a nanowire device, comprising:
removing a first sidewall spacer, thereby exposing at least a portion of each of a plurality of patterned semiconductor material layers; and
forming doped extension regions in at least said exposed portions of each of said patterned semiconductor material layers.

13. The method of claim 12 , wherein forming said doped extension regions comprises forming said doped extension regions such that said patterned semiconductor material layers have substantially the same dopant profile.

14. The method of claim 12 , further comprising forming a gate structure above said patterned semiconductor material layers.

15. The method of claim 12 , further comprising forming said first sidewall spacer adjacent to a gate structure.

16. The method of claim 12 , further comprising forming a second sidewall spacer adjacent to said first sidewall spacer.

17. The method of claim 12 , further comprising patterning said semiconductor material layers such that each layer has first and second exposed end surfaces.

18. The method of claim 12 , further comprising removing a second sidewall spacer, thereby exposing at least a portion of said patterned semiconductor material layers.

19. The method of claim 12 , further comprising recessing at least a first of said semiconductor material layers relative to a second of said semiconductor material layers.

Assignees

• Globalfoundries Inc

Inventors

• Koh Shao-Ming
• Bouche Guillaume
• Wan Jing
• Wei Andy C

Classifications

• H10P32/1204

  from a plasma phase · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title