Formation of semiconductor arrangement comprising buffer layer and semiconductor column overlying buffer layer

Patent metadata

Field	Value
Publication number	US-9490331-B2
Application number	US-201414318753-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A semiconductor arrangement and methods of formation are provided. A semiconductor arrangement includes a semiconductor column on a buffer layer over a substrate. The buffer layer comprises a conductive material. Both a first end of the semiconductor column and a bottom contact are connected to a buffer layer such that the first end of the semiconductor column and the bottom contact are connected to one another through the buffer layer, which reduces a contact resistance between the semiconductor column and the bottom contact. A second end of the semiconductor column is connected to a top contact. In some embodiments, the first end of the semiconductor column corresponds to a source or drain of a transistor and the second end corresponds to the a drain or source of the transistor.

First claim

What is claimed is:

1. A method of forming a semiconductor arrangement, comprising:
forming a buffer layer over a substrate;
forming a first dielectric layer over the buffer layer;
forming a first opening in the first dielectric layer, the first opening exposing a first portion of the buffer layer;
forming a first semiconductor column in the first opening such that a first end of the first semiconductor column is connected to the buffer layer;
forming a first gate around a…

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Vellianitis Georgios

Classifications

• H10D84/016

  Electricity · mapped topic

• H10D84/0195

  Electricity · mapped topic

• H10D84/0172

  Electricity · mapped topic

• H10D84/0167

  Electricity · mapped topic

• H10D84/85

  Electricity · mapped topic