Semiconductor structure with silicon oxide layer having a top surface in the shape of plural hills and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9490316-B2
Application number	US-201414542672-A
Country	US
Kind code	B2
Filing date	Nov 17, 2014
Priority date	Nov 17, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, a silicon oxide layer disposed on the substrate, and at least part of a gate electrode covering the silicon oxide layer. A top surface of the silicon oxide layer is in the shape of plural hills. The silicon oxide layer can provide low on-state resistance for the semiconductor structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate;
a silicon oxide layer disposed on the substrate, wherein a top surface of the silicon oxide layer is in a shape of plural hills, and a valley is disposed between each two adjacent hills; and
at least part of a gate electrode covering at least one of the hills and the valley.

2. The semiconductor structure of claim 1 , wherein each of the hills is table-shaped.

3. The semiconductor structure of claim 1 , wherein each of the hills is breast-shaped.

4. The semiconductor structure of claim 1 , wherein the silicon oxide layer further comprises a bottom surface which is symmetric to the top surface.

5. The semiconductor structure of claim 1 , wherein the gate electrode covers the silicon oxide layer entirely.

6. The semiconductor structure of claim 1 , further comprising an LDMOS disposed on the substrate, wherein a gate oxide layer of the LDMOS is asymmetric, and the gate oxide layer of the LDMOS comprises a LOCOS oxide layer.

7. The semiconductor structure of claim 1 , further comprising an FDMOS disposed on the substrate, wherein an STI is disposed directly under a gate electrode of the FDMOS.

8. The semiconductor structure of claim 1 , further comprising a low voltage MOS disposed on the substrate, wherein a gate oxide layer of the low voltage MOS has a thickness smaller than 80 Angstroms.

9. The semiconductor structure of claim 1 , wherein a vertical distance is disposed between the valley and a highest point of the hills, and the vertical distance is smaller than half of a greatest thickness of the silicon oxide layer.

10. A fabricating method of a semiconductor structure, comprising:
providing a substrate;
forming a plurality of first masks on the substrate; and
oxidizing the substrate to form a silicon oxide layer having a top surface comprising at least two hills and at least one valley, wherein the valley is disposed between the two adjacent hills, wherein the hills and the valley are formed simultaneously.

11. The fabricating method of a semiconductor structure of claim 10 , wherein the number of the first masks is more than three.

12. The fabricating method of a semiconductor structure of claim 10 , further comprising a first space disposed between two adjacent first masks, wherein the first space is between 0.1˜0.2 μm.

Assignees

• United Microelectronics Corp

Inventors

• Yang Ching-Chung
• Hsiao Shih-Yin

Classifications

• H10W10/0124

  the regions having non-rectangular shapes, e.g. rounded (H10W10/0123 takes precedence) · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title