Half select method and structure for gating rashba or spin hall MRAM

Patent metadata

Field	Value
Publication number	US-9490297-B1
Application number	US-201514871118-A
Country	US
Kind code	B1
Filing date	Sep 30, 2015
Priority date	Sep 30, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

The present disclosure generally relates to SHE-MRAM memory cells. A memory cell array comprises one or more memory cells, wherein each of the one or more memory cells comprises a gate electrode, an insulating layer, a spin orbit material electrode, a MTJ, and a top electrode parallel to the gate electrode. The gate electrode and the top electrode are perpendicular to the spin orbit material electrode. By applying a voltage to the gate electrode, passing a current along the spin orbit material electrode, and utilizing Rashba and/or spin hall effects, writability of select memory cells is enhanced, allowing for individual memory cells to be written upon without disturbing neighboring memory cells. Additionally, Rashba and/or spin hall effects in neighboring memory cells may be suppressed to ensure only the selected memory cell is written.

First claim

What is claimed is:

1. A memory cell array, comprising:
a first gate electrode;
a first top electrode disposed above and parallel to the first gate electrode;
a first memory cell disposed between the first gate electrode and the first top electrode;
a second memory cell disposed between the first gate electrode and the first top electrode, and wherein the second memory cell is disposed adjacent to and spaced from the first memory cell;
a second gate electrode disposed adjacent and parallel to the first gate electrode;
a first spin orbit material electrode disposed perpendicular to the first gate electrode and the second gate electrode, wherein the first spin orbit material electrode is disposed between the first gate electrode and the first memory cell; and
a third memory cell disposed on the first spin orbit material electrode and the second gate electrode, wherein the third memory cell is disposed adjacent to and spaced from the first memory cell, wherein the first memory cell, the second memory cell, and the third memory cell each comprise a free layer, a barrier layer disposed on the free layer, and a fixed layer disposed on the barrier layer.

2. The memory cell array of claim 1 , wherein the memory cell array is a spin-hall-effect-based magnetoresistive random access memory array.

3. The memory cell array of claim 1 , wherein the first spin orbit material electrode comprises a material having an atomic number between 30 and 85.

4. The memory cell array of claim 3 , wherein the first spin orbit material electrode comprises mercury-telluride, or indium-gallium-arsenide.

5. The memory cell array of claim 1 , wherein the free layer of the first memory cell is directly disposed on and in contact with the first spin orbit material electrode, and the free layer of the third memory cell is directly disposed on and in contact with the first spin orbit material electrode.

6. The memory cell array of claim 1 , further comprising a second spin orbit material electrode disposed perpendicular to the first gate electrode and the second gate electrode, wherein the second spin orbit material layer is disposed between the second memory cell and the first gate electrode and is parallel to and spaced from the first spin orbit material electrode.

7. The memory cell array of claim 6 , wherein the first spin orbit material electrode and the second spin orbit material electrode are word lines.

8. The memory cell array of claim 7 , wherein the first gate electrode is a write line, the second gate electrode is a write line, and the top electrode is a bit line.

9. The memory cell array of claim 8 , further comprising a fourth gate electrode disposed above the third gate electrode and the third memory cell, wherein the fourth gate electrode is a bit line.

10. The memory cell array of claim 1 , further comprising an insulating layer disposed between the first spin orbit material electrode and the first gate electrode, and between the first spin orbit material electrode and the third gate electrode.

Assignees

• HGST Netherlands BV

Inventors

• Braganca Patrick M
• Fidelis Garcia Andrei Gustavo

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• G11C11/18

  using Hall-effect devices · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title