Array substrate and method for producing the same and display apparatus

Patent metadata

Field	Value
Publication number	US-9490266-B2
Application number	US-201514740943-A
Country	US
Kind code	B2
Filing date	Jun 16, 2015
Priority date	Feb 3, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Embodiments of the present invention relate to the display field and provide an array substrate, a method for producing the same and a display apparatus, for reducing a via hole space without adding a step for patterning the gate insulation layer and thereby reducing product costs. The array substrate includes a gate metal layer, a gate insulation layer, a source and drain metal layer and a passivation layer, wherein the array substrate is provided with a via hole, which passes through the passivation layer, the source and drain metal layer and the gate insulation layer and at which a transparent conductive material is deposited for connecting the source and drain metal layer with the gate metal layer.

First claim

What is claimed is:

1. An array substrate comprising:
a first metal layer forming a gate electrode,
a gate insulation layer,
a second metal layer forming source and drain electrodes,
a passivation layer,
a pixel electrode, and
a common electrode,
wherein the array substrate is provided with a via hole, which passes through the passivation layer, the second metal layer forming the source and drain electrodes and the gate insulation layer and at which transparent conductive material is deposited for connecting the second metal layer forming the source and drain electrodes with the first metal layer forming the gate electrode, and wherein the transparent conductive material at the via hole and the common electrode are both formed by the same transparent conductive layer.

2. The array substrate according to claim 1 , wherein, the via hole which passes through the passivation layer, the second metal layer forming the source and drain electrodes and the gate insulation layer is formed by:
depositing the gate insulation layer;
depositing the second metal layer forming the source and drain electrodes and patterning it to form a pattern including the via hole in the second metal layer forming the source and drain electrodes;
depositing the passivation layer;
patterning the passivation layer and etching the passivation layer and the gate insulation layer at the via hole to form a pattern including the via hole.

3. A display apparatus, comprising: an array substrate, the array substrate comprising a first metal layer forming a gate electrode, a gate insulation layer, a second metal layer forming source and drain electrodes, a passivation layer, a pixel electrode and a common electrode, wherein the array substrate is provided with a via hole, which passes through the passivation layer, the second metal layer forming the source and drain electrodes and the gate insulation layer and at which a transparent conductive material is deposited for connecting the second metal layer forming the source and drain electrodes with the first metal layer forming the gate electrode, and wherein the transparent conductive material at the via hole and the common electrode are both formed by the same transparent conductive layer.

4. The display apparatus according to claim 3 , wherein the via hole which passes through the passivation layer, the second metal layer forming the source and drain electrodes and the gate insulation layer is formed by:
depositing the gate insulation layer;
depositing the second metal layer forming the source and drain electrodes and patterning it to form a pattern including the via hole in the second metal layer for forming the source and drain electrodes;
depositing the passivation layer;
patterning the passivation layer and etching the passivation layer and the gate insulation layer at the via hole to form a pattern including the via hole.

5. A method for producing an array substrate, the method comprising:
depositing a first metal layer forming a gate electrode on a substrate and patterning the first metal layer forming the gate electrode to form a patterned metal layer forming the gate electrode;
depositing a gate insulation layer;
depositing a second metal layer forming source and drain electrodes and patterning it to form a pattern including a via hole in the second metal layer forming the source and drain electrodes;
depositing a passivation layer;
patterning the passivation layer and etching the passivation layer and the gate insulation layer at the via hole to form a pattern including the via hole passing through the passivation layer, the second metal layer for forming the source and drain electrodes and the gate insulation layer; and
depositing a transparent conductive film and patterning it to form a patterned transparent conductive layer, the patterned transparent conductive layer including a transparent conductive material at the via hole, the transparent conductive material at the via hole being configured to connect the second metal layer forming the source and drain electrodes with the first metal layer forming the gate electrode,
wherein the patterned transparent conductive layer further comprises a common electrode and a pixel electrode, and a transparent conductive material at the via hole and the common electrode are formed at the same step.

6. The method according to claim 5 , wherein the transparent conductive material at the via hole and the pixel electrode are formed in different layers respectively.

7. The method according to claim 5 , further comprising:
depositing and patterning an active layer after depositing the gate insulation layer and before depositing the second metal layer forming the source and drain electrodes.

Assignees

• Boe Technology Group Co Ltd
• Chongqing Boe Optoelectronics Technolgy Co Ltd
• Chongqing Boe Optoelectronics Tech Co Ltd

Inventors

• Wang Wu
• Qiu Haijun
• Shang Fei
• Wang Guolei
• Wang Rui

Classifications

• H01L27/127

  Electricity · mapped topic

• H01L27/1222 Primary

  Electricity · mapped topic

• H01L27/15

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic