Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9490265-B2
Application number	US-201514693886-A
Country	US
Kind code	B2
Filing date	Apr 23, 2015
Priority date	Mar 13, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate having a metal-oxide semiconductor (MOS) transistor thereon, and an oxide semiconductor transistor adjacent to the MOS transistor. Preferably, the MOS transistor includes a first gate structure and a source/drain region adjacent to two sides of the gate structure, and the oxide semiconductor transistor includes a channel layer and the top surface of the channel layer is lower than the top surface of the first gate structure of the MOS transistor.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
providing a substrate having a metal-oxide semiconductor (MOS) transistor thereon, wherein the MOS transistor comprises a first gate structure and a source/drain region adjacent to two sides of the first gate structure;
forming a contact etch stop layer (CESL) on the first gate structure and the source/drain region;
forming an oxide semiconductor transistor on the CESL and adjacent to the MOS transistor, wherein the oxide semiconductor transistor comprises a channel layer and the top surface of the channel layer is lower than the top surface of the first gate structure of the MOS transistor.

2. The method of claim 1 , further comprising:
forming the contact etch stop layer (CESL) on the MOS transistor and the substrate;
forming the channel layer on the CESL;
forming a source layer and a drain layer on the CESL and adjacent to the channel layer;
forming a gate insulating layer on the CESL, the source layer, the drain layer, and the channel layer; and
forming a second gate structure on the channel layer.

3. The method of claim 2 , further comprising forming an interlayer dielectric (ILD) layer on the CESL and the second gate structure.

4. The method of claim 3 , further comprising forming a plurality of contact plugs in the ILD layer, the gate insulating layer, and the CESL for electrically connecting to the second gate structure, the source layer, the drain layer, and the source/drain region of the MOS transistor.

5. The method of claim 1 , wherein the oxide semiconductor layer is selected from the group consisting of indium gallium zinc oxide (IGZO), indium aluminum zinc oxide, indium tin zinc oxide, indium aluminum gallium zinc oxide, indium tin aluminum zinc oxide, indium tin hafnium zinc oxide, and indium hafnium aluminum zinc oxide.

6. A semiconductor device, comprising:
a substrate having a metal-oxide semiconductor (MOS) transistor thereon, wherein the MOS transistor comprises a first gate structure and a source/drain region adjacent to two sides of the gate structure;
a contact etch stop layer (CESL) on the first gate structure and the source/drain region; and
an oxide semiconductor transistor on the CESL and adjacent to the MOS transistor, wherein the oxide semiconductor transistor comprises a channel layer and the top surface of the channel layer is lower than the top surface of the first gate structure of the MOS transistor.

7. The semiconductor device of claim 6 , further comprising the contact etch stop layer (CESL) on the MOS transistor and the substrate.

8. The semiconductor device of claim 7 , wherein the channel layer is on the CESL.

9. The semiconductor device of claim 8 , further comprising:
a source layer and a drain layer on the CESL and the channel layer;
a gate insulating layer on the CESL, the source layer, the drain layer, and the channel layer; and
a second gate structure on the gate insulating layer.

10. The semiconductor device of claim 9 , further comprising an interlayer dielectric (ILD) layer on the MOS transistor and the gate insulating layer.

11. The semiconductor device of claim 10 , further comprising a plurality of contact plugs in the ILD layer, the gate insulating layer, and the CESL for electrically connecting to the second gate structure, the source layer, the drain layer, and the source/drain region of the MOS transistor.

12. The semiconductor device of claim 6 , wherein the bottom surface of the channel layer is higher than the bottom surface of the first gate structure.

13. The semiconductor device of claim 6 , wherein the channel layer is selected from the group consisting of indium gallium zinc oxide (IGZO) , indium aluminum zinc oxide, indium tin zinc oxide, indium aluminum gallium zinc oxide, indium tin aluminum zinc oxide, indium tin hafnium zinc oxide, and indium hafnium aluminum zinc oxide.

Assignees

• United Microelectronics Corp

Inventors

• Hsu Chia-Fu

Classifications

• H10P14/36

  characterised by treatments done before the formation of the materials · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/38

  characterised by treatments done after the formation of the materials · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title