Power cell, power cell circuit for a power amplifier and a method of making and using a power cell

Patent metadata

Field	Value
Publication number	US-9490248-B2
Application number	US-201313753995-A
Country	US
Kind code	B2
Filing date	Jan 30, 2013
Priority date	Dec 31, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer.

First claim

What is claimed is:

1. A power cell comprising:
an isolation region having a first dopant type in a substrate;
a bottom gate having a second dopant type different from the first dopant type on the isolation region;
a channel layer having the first dopant type on the bottom gate;
source/drain regions having the first dopant type on the channel layer, wherein the channel layer is physically continuous between the source/drain regions;
a first well region having the second dopant type around the channel layer and the source/drain regions, the first well region electrically connected to the bottom gate;
a second well region having the first dopant type around the channel layer and contacting the isolation region; and
a gate structure on the channel layer, wherein the gate structure comprises:
a gate dielectric layer, wherein a bottom-most surface of the gate dielectric layer is on a top-most surface of the channel layer, and the gate dielectric layer exposes an entirety of the source/drain regions, and
a gate electrode over the gate dielectric layer.

2. The power cell of claim 1 , wherein the first dopant type is an n-type dopant and the second dopant type is a p-type dopant.

3. The power cell of claim 1 , wherein the gate dielectric layer has a thickness ranging from 60 Angstroms (Å) to 80 Å.

4. The power cell of claim 1 , further comprising:
a resistor having a first side electrically connected to the first well region; and
a bias source electrically connected to a second side of the resistor.

5. The power cell of claim 4 , wherein the resistor has a resistance greater than or equal to 5K ohm-cm.

6. The power cell of claim 1 , wherein the substrate has a resistance greater than or equal to 5K ohm-cm.

7. The power cell of claim 1 , further comprising non-conductive regions between the source/drain regions and the first well region.

8. The power cell of claim 1 , wherein a dopant concentration of the first well region is equal to or greater than a dopant concentration of the bottom gate.

9. The power cell of claim 1 , wherein the channel layer, the source/drain regions, the gate structure and the bottom gate form a three-dimensional channel.

10. The power cell of claim 1 , wherein the gate dielectric layer comprises a dielectric material having a dielectric constant higher than a dielectric constant of silicon dioxide.

11. The power cell of claim 10 , wherein the dielectric constant of the dielectric material is greater than 3.9.

12. A power circuit comprising:
a first device, the first device configured to receive a power supply and a first input signal and to output a first output signal; and
a second device, the second device configured to receive a second input signal and the first output signal and to output a second output signal, the second device comprising:
an isolation region having a first dopant type in a substrate;
a bottom gate having a second dopant type different from the first dopant type on the isolation region;
a channel layer having the first dopant type on the bottom gate;
source/drain regions having the first dopant type on the channel layer, wherein the source/drain regions have a top surface substantially level with a top surface of the channel layer;
a first well region having the second dopant type around the channel layer and the source/drain regions, the first well region electrically connected to the bottom gate;
a second well region having the first dopant type around the channel layer and contacting the isolation region;
a gate structure on the top surface of the channel layer, wherein the gate structure is on an upper-most surface of the channel layer; and
a first resistor electrically connected between the first well region and a first bias source.

13. The power circuit of claim 12 , wherein the first input signal and the second input signal are the same.

14. The power circuit of claim 12 , wherein the first input signal is different from the second input signal.

15. The power circuit of claim 12 , further comprising a second resistor electrically connected to the gate structure of the second device configured to receive the second input signal.

16. The power circuit of claim 12 , wherein a resistance of the first resistor is equal to or greater than 5K ohm-cm.

17. The power circuit of claim 12 , wherein the gate structure comprises:
a gate dielectric layer over the channel layer; and
a gate electrode over the gate dielectric layer.

18. The power circuit of claim 12 , wherein the gate structure comprises a metal layer and the metal layer and the channel layer form a Schottky diode.

19. The power circuit of claim 12 , wherein the first device comprises:
a second isolation region having the first dopant type in the substrate;
a second bottom gate having the second dopant type on the second isolation region;
a second channel layer having the first dopant type on the second bottom gate;
second source/drain regions having the first dopant type on the second channel layer;
a second first well region having the second dopant type around the second channel layer and the second source/drain regions, and the second first well region electrically connected to the second bottom gate;
a second second well region having the first dopant type around the second channel layer and contacting the isolation region; and
a second gate structure on the second channel layer.

20. A method of making a power cell, the method comprising:
forming an isolation region having a first dopant type;
forming a bottom gate having a second dopant type different from the first dopant type on the isolation region;
forming a channel layer having the first dopant type on the bottom gate;
forming a gate dielectric layer over the channel layer;
forming a gate electrode over the gate dielectric layer;
forming source/drain regions having the first dopant type in the channel layer, wherein sidewalls of the source/drain regions directly contact the channel layer, and the gate dielectric layer exposes an entirety of the source/drain regions;
forming a first well region having the second dopant type around the channel layer and the source/drain regions, the first well region electrically connected to the bottom gate;
forming a second well region having the first dopant type around the channel layer and contacting the isolation region; and
forming a gate structure on the channel layer, wherein a bottom surface of the gate structure is above a top surface of the source/drain regions.

21. The method of claim 20 , wherein the first dopant type is an n-type dopant and the second dopant type is a p-type dopant.

22. The method of claim 20 , wherein forming the gate dielectric layer comprises forming the gate dielectric layer having a thickness ranging from 60 Angstroms (Å) to 80 Å.

23. The method of claim 20 , further comprising:
electrically connecting a resistor to the first well region.

24. The method of claim 20 , further comprising forming non-conductive regions between the source/drain regions and the first well region.

25. The method of claim 20 , wherein forming the first well region comprises forming the first well region having a dopant concentration equal to or greater than a dopant concentration of the bottom gate.

26. The method of claim 20 , wherein forming the channel layer, the source/drain regions, the gate structure and the bottom gate comprise

Assignees

• Yeh Tzu-Jin
• Jou Chewn-Pu
• Jin Jun-De
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeh Tzu-Jin
• Jou Chewn-Pu
• Jin Jun-De

Classifications

• H10D62/021

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title

• H10D62/378

  Contact regions to the substrate regions · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/615

  comprising a MOS gate electrode and at least one non-MOS gate electrode · CPC title

• H10D30/023

  having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031) · CPC title