Two-terminal integrated circuit device for electrostatic discharge protection
US-2024413147-A1 · Dec 12, 2024 · US
Semiconductor device comprising an ESD protection device, an ESD protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device
US9490243B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9490243-B2 |
| Application number | US-201214419064-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 22, 2012 |
| Priority date | Aug 22, 2012 |
| Publication date | Nov 8, 2016 |
| Grant date | Nov 8, 2016 |
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- Title
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- Abstract
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Abstract
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A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region.
First claim
Opening claim text (preview).
The invention claimed is: 1. A semiconductor device comprising an ESD protection device for protecting an integrated circuit on the semiconductor device against ESD event received by the integrated circuit, the ESD protection device comprising a semiconductor substrate, the semiconductor substrate having a first side, the semiconductor substrate having an N-buried region extending in a lateral direction in the interior of the semiconductor substrate, a p-doped isolated portion o…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9490243B2 cover?
- A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The …
- Who is the assignee on this patent?
- Laine Jean Philippe, Besse Patrice, Freescale Semiconductor Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D89/711. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).