Semiconductor device comprising a first inverter and a second inverter

Patent metadata

Field	Value
Publication number	US-9490241-B2
Application number	US-201213533113-A
Country	US
Kind code	B2
Filing date	Jun 26, 2012
Priority date	Jul 8, 2011
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A semiconductor device which is downsized while a short-channel effect is suppressed and whose power consumption is reduced is provided. A downsized SRAM circuit is formed, which includes a first inverter including a first transistor and a second transistor overlapping with each other; a second inverter including a third transistor and a fourth transistor overlapping with each other; a first selection transistor; and a second selection transistor. An output terminal of the first inverter, an input terminal of the second inverter, and one of a source and a drain of the first selection transistor are connected to one another, and an output terminal of the second inverter, an input terminal of the first inverter, and one of a source and a drain of the second selection transistor are connected to one another.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a first inverter; and
a second inverter,
wherein an output terminal of the first inverter is electrically connected to an input terminal of the second inverter,
wherein an output terminal of the second inverter is electrically connected to an input terminal of the first inverter,
wherein each of the first inverter and the second inverter comprises a first transistor and a second transistor,
wherein the first transistor comprises:
the semiconductor substrate having a source region and a drain region, wherein the semiconductor substrate has a groove portion arranged between the source region and the drain region;
a first gate insulating film formed on a side surface and a bottom surface of the groove portion; and
a gate electrode formed in the groove portion with the first gate insulating film provided between the semiconductor substrate and the gate electrode, wherein the first transistor and the second transistor share the gate electrode, and

wherein the second transistor comprises:
a second gate insulating film covering the gate electrode;
a semiconductor film overlapping with the gate electrode with the second gate insulating film provided therebetween; and
a pair of electrodes in contact with the semiconductor film,

wherein the pair of electrodes is formed between the second gate insulating film and the semiconductor film.

2. The semiconductor device according to claim 1 , further comprising:
a first selection transistor; and
a second selection transistor,
wherein one of a source and a drain of the first selection transistor is electrically connected to the output terminal of the first inverter and the input terminal of the second inverter,
wherein one of a source and a drain of the second selection transistor is electrically connected to the output terminal of the second inverter and the input terminal of the first inverter,
wherein gates of the first selection transistor and the second selection transistor are electrically connected to a first line,
wherein the other of the source and the drain of the first selection transistor is electrically connected to a second line, and
wherein the other of the source and the drain of the second selection transistor is electrically connected to a third line.

3. The semiconductor device according to claim 1 ,
wherein the semiconductor substrate is an n-type semiconductor, and
wherein the source region and the drain region are each a p-type semiconductor.

4. The semiconductor device according to claim 1 , wherein the semiconductor film comprises an oxide semiconductor comprising one or more of elements selected from In, Ga, Sn, and Zn.

5. The semiconductor device according to claim 1 ,
wherein the first gate insulating film of the first inverter and the first gate insulating film of the second inverter are formed from a same film, and
wherein the second gate insulating film of the first inverter and the second gate insulating film of the second inverter are formed from a same film.

6. A semiconductor device comprising:
a semiconductor substrate comprising a pair of first low-resistance regions and a pair of second low-resistance regions, wherein a resistance of each of the pair of first low-resistance regions and the pair of second low-resistance regions is lower than a resistance of the semiconductor substrate;
a first insulating film overlapping with the semiconductor substrate;
a first conductive film overlapping with the semiconductor substrate with the first insulating film provided therebetween;
a second insulating film over the first conductive film;
a first semiconductor film overlapping with the first conductive film with the second insulating film provided therebetween;
a pair of first electrodes in contact with the first semiconductor film;
a third insulating film overlapping with the semiconductor substrate;
a second conductive film overlapping with the semiconductor substrate with the third insulating film provided therebetween;
a fourth insulating film over the second conductive film;
a second semiconductor film overlapping with the second conductive film with the fourth insulating film provided therebetween; and
a pair of second electrodes in contact with the second semiconductor film,
wherein the first conductive film, one of the pair of second low-resistance regions, and one of the pair of second electrodes are electrically connected to one another,
wherein the second conductive film, one of the pair of first low-resistance regions, and one of the pair of first electrodes are electrically connected to one another,
wherein the semiconductor substrate has a first groove portion between the pair of first low-resistance regions and a second groove portion between the pair of second low-resistance regions,
wherein the first insulating film is formed on a side surface and a bottom surface of the first groove portion,
wherein the first conductive film is formed in the first groove portion,
wherein the second insulating film is formed on a side surface and a bottom surface of the second groove portion, and
wherein the second conductive film is formed in the second groove portion.

7. The semiconductor device according to claim 6 , further comprising:
a first selection transistor; and
a second selection transistor,
wherein one of a source and a drain of the first selection transistor is electrically connected to the second conductive film, one of the pair of first low-resistance regions, and one of the pair of first electrodes,
wherein one of a source and a drain of the second selection transistor is electrically connected to the first conductive film, one of the pair of second low-resistance regions, and one of the pair of second electrodes,
wherein gates of the first selection transistor and the second selection transistor are electrically connected to a first line,
wherein the other of the source and the drain of the first selection transistor is electrically connected to a second line, and
wherein the other of the source and the drain of the second selection transistor is electrically connected to a third line.

8. The semiconductor device according to claim 6 ,
wherein the pair of first electrodes is formed between the second insulating film and the first semiconductor film, and
wherein the pair of second electrodes is formed between the fourth insulating film and the second semiconductor film.

9. The semiconductor device according to claim 6 ,
wherein the first semiconductor film is formed between the second insulating film and the pair of first electrodes, and
wherein the second semiconductor film is formed between the fourth insulating film and the pair of second electrodes.

10. The semiconductor device according to claim 6 ,
wherein the semiconductor substrate is an n-type semiconductor, and
wherein the pair of first low-resistance regions and the pair of second low-resistance regions are each a p-type semiconductor.

11. The semiconductor device according to claim 6 , wherein the first semiconductor film and the second semiconductor film each comprise an oxide semiconductor comprising one or more of elements selected from In, Ga, Sn, and Zn.

12. The semiconductor device according to claim 6 ,
wherein the first insulating film and the third insulating film are formed from a same film, and
wherein the second insulating film and the fourth insulating film are formed from a same film.

13. A semiconductor device comprising:
a semiconductor substrate;
a first inverter; and
a second inverter,
wherein an output terminal of

Assignees

• Nomura Masumi
• Nishijima Tatsuji
• Noda Kosei
• Semiconductor Energy Lab

Inventors

• Nomura Masumi
• Nishijima Tatsuji
• Noda Kosei

Classifications

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10B99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10B10/125 Primary

  the MOSFET being a thin film transistor [TFT] · CPC title

• H01L27/1108

  Electricity · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic