Self-aligned airgap interconnect structures

US9490202B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9490202-B2
Application numberUS-201414505087-A
CountryUS
Kind codeB2
Filing dateOct 2, 2014
Priority dateApr 15, 2011
Publication dateNov 8, 2016
Grant dateNov 8, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material, Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit device, comprising: at least a pair of conductive structures positioned on a substrate and configured by etching a conductive layer to form sidewalls extending through a thickness of the conductive layer; and a self-aligned airgap formed between the pair of conductive structures and being bounded by a permeable cap layer positioned on the pair of conductive structures and a conformal dielectric layer positioned in contact with the substrate and the sidewalls of each of the pair of conductive structures, wherein the conformal dielectric layer is not present on an upper surface of each of the pair of conductive structures. 2. The device as recited in claim 1 , wherein the permeable cap layer includes a dielectric material comprising one or more of Si, Ge, C, N, O, H. 3. The device as recited in claim 1 , wherein the substrate includes a semiconductor material or a conductive component of a lower layer. 4. The device as recited in claim 1 , wherein the at least a pair of conductive structures form single damascene structures. 5. The device as recited in claim 1 , wherein the at least a pair of conductive structures form dual damascene structures. 6. The device as recited in claim 1 , wherein the self-aligned airgap is formed between said conductive structures of said at least said pair of conductive structures in a single conductive layer. 7. The device as recited in claim 1 , wherein the self-aligned airgap is continuous and extends between said conductive structures of said at least said pair of conductive structures in multiple contact layers. 8. The device as recited in claim 1 , wherein the self-aligned airgap includes a stepped structure. 9. The device as recited in claim 1 , wherein the device includes linewidths less than 90 nm. 10. The device as recited in claim 1 , wherein the permeable cap layer extends over said self-aligned airgap from one sidewall to an opposing sidewall of the pair of conductive structures that bound the airgap, and wherein the permeable cap layer is present in direct contact with an upper surface of each of the pair of conductive structures.

Assignees

Inventors

Classifications

  • H10P50/286Primary

    of organic materials · CPC title

  • Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

  • Interconnections over air gaps, e.g. air bridges · CPC title

  • of dielectric parts comprising air gaps · CPC title

  • by forming conductive members before forming protective insulating material · CPC title

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What does patent US9490202B2 cover?
Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrific…
Who is the assignee on this patent?
Globalfoundries Inc, Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10P50/286. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).