Multi die package having a die and a spacer layer in a recess

Patent metadata

Field	Value
Publication number	US-9490196-B2
Application number	US-201113977183-A
Country	US
Kind code	B2
Filing date	Oct 31, 2011
Priority date	Oct 31, 2011
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

First claim

We claim:

1. A device comprising,
a packaging substrate having a surface wherein the surface has a recess formed therein,
a first integrated circuit die disposed in the recess of the packaging substrate wherein the first integrated circuit die has a surface,
a spacer layer disposed on the surface of the first integrated circuit die wherein the spacer layer has a first surface proximate to the first integrated circuit die and a second surface opposite to the first surface wherein the spacer layer is separate and distinct from the packaging substrate, and wherein the spacer layer is disposed in the recess, and
a second integrated circuit die bonded to the surface of the packaging substrate and to the second surface of the spacer layer.

2. The device of claim 1 wherein the packaging substrate is a coreless packaging substrate.

3. The device of claim 1 wherein the packaging substrate is comprised of build-up layers of dielectric and conducting materials.

4. The device of claim 1 wherein the second integrated circuit die is bonded with an epoxy material, a region of metal, a region of silicon, a region of silicon dioxide, or a region of silicon nitride.

5. The device of claim 1 wherein the first die is electrically coupled to the second die through conducting regions that extend from the surface of the first die to a surface of the second die.

6. The device of claim 1 wherein the spacer layer is comprised of a dielectric material selected from the group consisting of a composite of a polymer and inorganic material, silicon dioxide, silicon nitride, spin-on glass, and ceramic.

7. A device comprising,
a mainboard assembly having a first side, wherein the mainboard assembly has a package assembly disposed thereon and the package assembly comprises:
a packaging substrate having a surface wherein the surface has a recess formed therein,
a first integrated circuit die disposed in the recess of the packaging substrate wherein the first integrated circuit die has a surface,
a spacer layer disposed on the surface of the first integrated circuit die wherein the spacer layer has a first surface proximate to the first integrated circuit die and a second surface opposite to the first surface wherein the spacer layer is separate and distinct from the packaging substrate, and

wherein the spacer layer is disposed in the recess, and
a second integrated circuit die bonded to the surface of the coreless packaging substrate and to the second surface of the spacer layer.

8. The device of claim 7 wherein the packaging substrate is a coreless packaging substrate.

9. The device of claim 7 wherein the mainboard assembly has a second side, wherein the mainboard assembly has one or more additional devices disposed on the first or second side, and wherein the one or more additional devices are selected from the group consisting of processing devices, memory devices, signal processing devices, wireless communication devices, graphics controllers, input/output controllers, audio processors, power delivery components, and power management components.

Assignees

• Teh Weng Hong
• Guzek John S
• Zhong Shan
• Intel Corp

Inventors

• Teh Weng Hong
• Guzek John S
• Zhong Shan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/231

  the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title