Semiconductor device comprising a stacked die configuration including an integrated peltier element

Patent metadata

Field	Value
Publication number	US-9490189-B2
Application number	US-201414270941-A
Country	US
Kind code	B2
Filing date	May 6, 2014
Priority date	May 31, 2010
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

First claim

What is claimed:

1. A method of controlling temperature in a semiconductor device comprising a stacked device configuration, the method comprising:
providing a Peltier element that is distributed between circuit elements positioned in or above respective first and second substrates of said stacked device configuration, said Peltier element comprising:
a metal-based heat sink comprising a first wiring system formed above said first substrate of said stacked device configuration, said first wiring system connecting to a plurality of semiconductor regions formed in said first substrate via a front side of said first substrate; and
a metal-based heat source comprising a second wiring system formed above said second substrate of said stacked device configuration, said second wiring system connecting to said plurality of semiconductor regions formed in said first substrate through openings extending through said second substrate; and

establishing a current flow through said Peltier element when said semiconductor device is in a specified operating phase.

2. The method of claim 1 , wherein said first substrate comprises a central processing unit and said second substrate comprises a memory circuit.

3. The method of claim 1 , further comprising obtaining a temperature signal from said Peltier element and determining a thermal status of said semiconductor device by using said temperature signal.

4. The method of claim 1 , further comprising providing a control unit and using said control unit to control said current flow through said Peltier element.

5. The method of claim 4 , wherein controlling said current flow through said Peltier element comprises operating a switching system of said control unit so as to invert said current flow through said Peltier element, said inverted current flow inverting a direction of heat transfer in said semiconductor device.

6. The method of claim 4 , wherein providing said control unit comprises providing said control unit as a device external control unit outside of said stacked device configuration of said semiconductor device.

7. The method of claim 4 , wherein providing said control unit comprises providing said control unit as a device internal control unit that is formed on at least one of said first and second substrates.

8. The method of claim 4 , further comprising operating said Peltier element as a thermoelectric generator so as to provide electrical energy to said semiconductor device.

9. A method of controlling temperature in a semiconductor device comprising a plurality of stacked substrates, the method comprising:
providing a Peltier element comprising a metal-based heat sink formed above a first substrate of said plurality of stacked substrates and a metal-based heat source formed above a second substrate of said plurality of stacked substrates, said first substrate comprising a central processing unit and said second substrate comprising a memory circuit, wherein said metal-based heat sink formed above said first substrate comprises a first wiring system connecting to a plurality of semiconductor regions formed in said first substrate via a front side of said first substrate, and wherein said metal-based heat source formed above said second substrate comprises a second wiring system connecting to said plurality of semiconductor regions through openings extending through said second substrate;
operatively coupling a control unit to said Peltier element; and
controlling a current flow through said Peltier element with said control unit.

10. The method of claim 9 , wherein controlling said current flow through said Peltier element comprises at least one of establishing said current flow through said Peltier element or discontinuing said current flow through said Peltier element when said semiconductor device is in a specified operating phase.

11. The method of claim 9 , wherein controlling said current flow through said Peltier element comprises obtaining a temperature signal from said Peltier element and using said temperature signal to determine a thermal status of said semiconductor device.

12. The method of claim 9 , wherein controlling said current flow through said Peltier element comprises inverting said current flow through said Peltier element so as to invert a direction of heat transfer in said semiconductor device.

13. The method of claim 9 , wherein operatively coupling said control unit to said Peltier element comprises providing said control unit as a device external control unit outside of said semiconductor device.

14. The method of claim 9 , wherein operatively coupling said control unit to said Peltier element comprises providing said control unit as a device internal control unit that is formed on at least one of said first and second ones of said stacked substrates.

15. The method of claim 8 , further comprising operating said Peltier element as a thermoelectric generator so as to provide electrical energy to said semiconductor device.

16. The method of claim 9 , wherein controlling said current flow through said Peltier element comprises transferring heat from a first circuit comprising said first substrate of said plurality of stacked substrates to a second circuit comprising said second substrate of said plurality of stacked substrates, said first circuit having a higher power consumption than said second circuit.

17. The method of claim 1 , further comprising transferring heat from a first circuit comprising said first substrate of said stacked device configuration to a second circuit comprising said second substrate of said stacked device configuration, said first circuit having a higher power consumption than said second circuit.

18. A method of controlling temperature in a semiconductor device comprising a stacked device configuration, the method comprising:
providing a Peltier element that is distributed between circuit elements positioned in or above respective first and second substrates of said stacked device configuration, said Peltier element comprising:
a metal-based heat sink comprising a first wiring system formed above said first substrate of said stacked device configuration, wherein said first wiring system comprises a plurality of first connections that each connect one of a plurality of first semiconductor regions formed in said first substrate with one of a plurality of second semiconductor regions formed in said first substrate; and
a metal-based heat source comprising a second wiring system formed above said second substrate of said stacked device configuration, wherein said second wiring system comprises a plurality of second connections that each connect one of said plurality of first semiconductor regions with one of said plurality of second semiconductor regions; and

establishing a current flow through said Peltier element when said semiconductor device is in a specified operating phase.

19. The method of claim 18 , wherein said first and second semiconductor regions formed in said first substrate have different conduction band energy levels.

20. The method of claim 18 , wherein said circuit elements positioned in or above said first substrate comprise a central processing unit, and wherein said circuit elements positioned in or above said second substrate comprise a memory circuit.

Assignees

• Globalfoundries Inc

Inventors

• Griebenow Uwe
• Hoentschel Jan
• Scheiper Thilo
• Beyer Sven

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W40/28 Primary

  comprising Peltier coolers · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• G06F1/20

  Cooling means · CPC title