Compute intensive module packaging

US9490188B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9490188-B2
Application numberUS-201414485225-A
CountryUS
Kind codeB2
Filing dateSep 12, 2014
Priority dateSep 12, 2014
Publication dateNov 8, 2016
Grant dateNov 8, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A package for a multi-chip module includes a top cold plate and a bottom plate whose perimeters are in thermal communication so the plates together completely encase the module except for a connector passing through the bottom plate. The cold plate has copper tubing pressed into a groove formed in a serpentine pattern. The perimeter of the cold plate has thermal conduction fins which mate with thermal conduction slots in the perimeter of the bottom plate. Thermal interface material is disposed in gaps between the plates and chips on the module, the gaps having dimensions controlled by support ribs of plates which abut the module substrate. The cold plate is used on the hottest side of the module, e.g., the side having computationally-intensive chips such as ASICs. A densely packed array of these packages can be used in a central electronic complex drawer with a shared coolant circulation system.

First claim

Opening claim text (preview).

What is claimed is: 1. A package for an integrated circuit chip module comprising: a generally planar substrate having first and second opposing surfaces; a plurality of integrated circuit chips mounted on said first surface of said substrate; a first heat sink provided with a plurality of pockets to accommodate and provide thermal communication with said plurality of integrated circuit chips, said first heat sink having sides forming a perimeter; a second heat sink located opposite said first heat sink with respect to said substrate, said second heat sink having sides forming a perimeter which is in continuous direct contact with the perimeter of said first heat sink such that said first and second heat sinks together substantially surrounding said integrated circuit chips on all sides; and thermal interface material disposed in a gap between said first heat sink and the at least one of said plurality of integrated circuit chips, wherein said gap has a dimension which is determined by at least one support rib of said first heat sink which forcibly abuts said substrate. 2. The package of claim 1 wherein said first heat sink is a cold plate. 3. The package of claim 2 wherein said cold plate has first and second opposing surfaces, said first surface of said cold plate being in thermal communication with the at least one of said plurality of integrated circuit chips, said second surface of said cold plate having a groove formed therein in a serpentine pattern, and copper tubing pressed into said groove to receive a circulating coolant. 4. The package of claim 1 wherein a perimeter of said first heat sink has one or more thermal conduction fins which mate with one or more corresponding thermal conduction slots formed along a perimeter of said second heat sink. 5. The package of claim 4 further comprising thermal interface material disposed in a gap between one of said thermal conduction fins and one of said thermal conduction slots. 6. The package of claim 1 wherein said second heat sink has at least one alignment pin which extends through a hole in said substrate and into a socket of said first sink. 7. The package of claim 1 wherein the integrated circuit chips are a first plurality of integrated circuit chips, and further comprising a second plurality of integrated circuit chips mounted on said second surface of said substrate. 8. The package of claim 7 wherein the first plurality of integrated circuit chips include one or more processor chips, and the second plurality of integrated circuit chips include one or more power converters which supply power to said one or more processor chips. 9. A multi-chip module package comprising: a generally rectangular, planar substrate having top and bottom surfaces; a first plurality of integrated circuit chips mounted on said top surface of said substrate, said top surface having first connection features formed thereon which are operatively interconnected with first connection points of said first plurality of integrated circuit chips; a second plurality of integrated circuit chips mounted on said bottom surface of said substrate, said bottom surface having second connection features formed thereon which are operatively interconnected with second connection points of said second plurality of integrated circuit chips; a connector block mounted on said bottom surface of said substrate for interconnecting external connection features with said first and second connection features; a generally rectangular top cold plate disposed parallel with said substrate and provided with a first plurality of pockets to accommodate and provide thermal communication with said first plurality of integrated circuit chips, said top cold plate having a first compartment to accommodate said first plurality of integrated circuit chips, said first compartment having a perimeter; and a generally rectangular bottom heat dissipation plate disposed parallel with said substrate and located opposite said top cold plate with respect to said substrate and provided with a second plurality of pockets to accommodate and provide thermal communication with said second plurality of integrated circuit chips, said connector block passing through a connector cutout in said bottom heat dissipation plate, said bottom heat dissipation plate having a second compartment to accommodate said second plurality of integrated circuit chips, said second compartment having a perimeter, the perimeter of said first compartment being in direct contact with the perimeter of said second compartment to create a thermal conduction path from said bottom heat dissipation plate to said top cold plate along the entirety of the perimeters such that said top cold plate and said bottom heat dissipation plate together completely encase said first and second pluralities of integrated circuit chips except for the connector cutout. 10. The multi-chip module package of claim 9 wherein said cold plate has first and second opposing surfaces, said first surface of said cold plate being in thermal communication with the at least one of said first plurality of integrated circuit chips, said second surface of said cold plate having a groove formed therein in a serpentine pattern, said groove having copper tubing pressed therein to receive a circulating coolant, said copper tubing having first and second ends with said first end in fluid communication with a first manifold block located at a first corner of said cold plate and said second end in fluid communication with a second manifold block located at a second corner of said cold plate opposite said first corner. 11. The multi-chip module package of claim 9 further comprising a planar board connected to said connector block. 12. The multi-chip module package of claim 9 wherein the perimeter of said cold plate has one or more thermal conduction fins which mate with one or more corresponding thermal conduction slots formed along the perimeter of said bottom heat dissipation plate, and further comprising thermal interface material disposed in a gap between one of said thermal conduction fins and one of said thermal conduction slots. 13. The multi-chip module package of claim 9 wherein said substrate is held between said cold plate and said bottom heat dissipation plate using support ribs of said cold plate and said bottom heat dissipation plate which forcibly abut portions of said substrate, and said cold plate is secured to said bottom heat dissipation plate. 14. The multi-chip module package of claim 13 further comprising first thermal interface material disposed in a first gap between said cold plate and the at least one of said first plurality of integrated circuit chips, and second thermal interface material disposed in a second gap between said bottom heat dissipation plate and the at least one of said second plurality of integrated circuit chips, wherein said gaps have dimensions which are determined by said support ribs. 15. The multi-chip module package of claim 9 wherein the at least one of said first plurality of integrated circuit chips includes a computationally-intensive chip which generates more heat than any of the second plurality of integrated circuit chips. 16. A central electronic complex drawer for a computer system comprising: a chassis; a planar board supported by said chassis; a plurality of multi-chip module (MCM) packages mounted on said planar board in an array of rows and columns, each MCM package having a planar substrate with top and bottom surfaces, a first plurality of integrated circuit chips mounted on said top surface of said substrate, a s

Assignees

Inventors

Classifications

  • Fillings or auxiliary members in containers or in encapsulations for thermal protection or control · CPC title

  • by flowing liquids, e.g. forced water cooling · CPC title

  • Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

  • H10W40/22Primary

    characterised by their shape, e.g. having conical or cylindrical projections · CPC title

  • Assembling printed circuits with electric components, e.g. with resistors · CPC title

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Frequently asked questions

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What does patent US9490188B2 cover?
A package for a multi-chip module includes a top cold plate and a bottom plate whose perimeters are in thermal communication so the plates together completely encase the module except for a connector passing through the bottom plate. The cold plate has copper tubing pressed into a groove formed in a serpentine pattern. The perimeter of the cold plate has thermal conduction fins which mate with …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W40/22. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).