Gate stack materials for semiconductor applications for lithographic overlay improvement

US9490116B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9490116-B2
Application numberUS-201514879043-A
CountryUS
Kind codeB2
Filing dateOct 8, 2015
Priority dateJan 9, 2015
Publication dateNov 8, 2016
Grant dateNov 8, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming a film layer on a substrate comprising: supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber; forming a plasma in the presence of the depositing gas mixture in the processing chamber; applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber; and rotating the substrate while depositing a film layer on the substrate. 2. The method of claim 1 , wherein applying current to the plasma profile modulator further comprises: applying current to an electrode disposed in a sidewall of the processing chamber. 3. The method of claim 1 , wherein applying current to the plasma profile modulator further comprises: applying current to an electrode disposed in the substrate support of the processing chamber. 4. The method of claim 1 , wherein the reacting gas is selected from a group consisting of oxygen containing gas, a nitrogen containing gas and a carbon containing gas. 5. The method of claim 4 , wherein the nitrogen containing gas is selected from a group consisting of N 2 , N 2 O, NO 2 , NH 3 , and N 2 H 2 . 6. The method of claim 1 , wherein applying current to the plasma profile modulator further comprises: applying current of between about 0.5 A and about 40 A to the processing chamber. 7. The method of claim 1 , wherein the film layer has a stress uniformity less than 50%. 8. The method of claim 1 , wherein rotating the substrate further comprises: rotating the substrate at a rotation speed between about 0 rpm and about 100 rpm. 9. The method of claim 1 , wherein rotating the substrate further comprises: rotating the substrate at between about 0 degrees and about 360 degrees around an axis of the substrate support. 10. The method of claim 1 , wherein the film layer is a silicon nitride layer. 11. A method for forming a film layer on a substrate comprising: controlling a plasma generated from a gas mixture in a processing chamber by applying current to a plasma profile modulator disposed in the processing chamber; and forming a film layer on a substrate with the controlled plasma, wherein the film layer has a local bow range less than 50 μm. 12. The method of claim 11 , wherein controlling the plasma further comprises: applying the current to an electrode disposed in a sidewall of the processing chamber. 13. The method of claim 11 , wherein controlling the plasma further comprises: applying the current to an electrode disposed in a substrate support disposed in the processing chamber. 14. The method of claim 11 , further comprising: rotating the substrate while forming the film layer on the substrate. 15. The method of claim 11 , wherein the gas mixture includes a silicon containing gas and a nitrogen containing gas. 16. The method of claim 11 , wherein the film layer is a silicon nitride layer. 17. A film structure comprising: a film stack includes a first film layer and a second film layer disposed on the first layer, wherein the first film layer and the second film layer are alternatively and repeatedly formed in the film stack with a total thickness between about 600 nm and about 4000 nm, wherein the film stack has a local bow range less than 200 μm. 18. The film structure of claim 17 , wherein the first film layer is a silicon oxide layer and the second film layer is a silicon nitride layer. 19. The film structure of claim 17 , wherein the film stack has about 5 to 90 pairs of alternating first film layers and the second film layers which is utilized to form 3D NAND gate structure for semiconductor devices. 20. The film structure of claim 17 , wherein the second film layer is formed by a plasma deposition process with a plasma distribution controlled by a plasma profile modulator disposed in a processing chamber.

Assignees

Inventors

Classifications

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

  • in the presence of a plasma [PECVD] · CPC title

  • Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

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What does patent US9490116B2 cover?
Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber,…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/6336. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).