Read tracking mechanism
US-2015078110-A1 · Mar 19, 2015 · US
Memory timing circuit
US9489994B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9489994-B2 |
| Application number | US-201615013605-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 2, 2016 |
| Priority date | Apr 10, 2014 |
| Publication date | Nov 8, 2016 |
| Grant date | Nov 8, 2016 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory circuit, comprising: a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a word-line circuit configured to control a word-line of the memory cell; a bit-line circuit having at least one of (i) a bit-line voltage control circuit and (ii) a mux circuit; and a sense amplifier comprising a local sense amplifier bias circuit, wherein the sense amplifier is configured to sense the charge, voltage, or current on the bit-line and locally control its local sense amplifier bias circuit by turning the local sense amplifier bias circuit OFF or placing it in low power state, upon determining that the charge, voltage, or current on the bit-line is above a predetermined threshold.
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Classifications
Timing of memory operations based on dummy memory elements or replica circuits · CPC title
Reading or sensing circuits or methods · CPC title
- G11C7/12Primary
Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title
Single-ended amplifiers · CPC title
Timing of a read operation · CPC title
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Frequently asked questions
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- What does patent US9489994B2 cover?
- A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control…
- Who is the assignee on this patent?
- Infineontechnologies Ag, Infineon Technologies Ag
- What technology area does this patent fall under?
- Primary CPC classification G11C7/12. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).