Systems, methods, and computer program products for performing mathematical operations

Patent metadata

Field	Value
Publication number	US-9489342-B2
Application number	US-201314127178-A
Country	US
Kind code	B2
Filing date	Jun 21, 2013
Priority date	Dec 24, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

The system has first, second, third, and fourth subsystems. Each subsystem has first and second multipliers coupled, respectively, to first and second adders. Each multiplier has two inputs. The first adder is coupled to a first output, a first accumulator, and a bit shifter. The bit shifter is coupled to a third adder. The third adder is coupled to a multiplexer. The multiplexer is coupled to a second output and a second accumulator. The second adder is coupled to the third adder and the multiplexer. The first outputs of the first and second subsystems are coupled directly to a fourth adder, the second outputs of the first and second subsystems are coupled directly to a fifth adder, the first outputs of the third and fourth subsystems are coupled directly to a sixth adder, and the second outputs of the third and fourth subsystems are coupled directly to a seventh adder.

First claim

What is claimed is:

1. A system for performing mathematical operations, comprising:
subsystems, wherein each subsystem is coupled to simulate a unique position defined by a first dimension coordinate and a second dimension coordinate, wherein sets of the subsystems are defined by the first dimension coordinate, and wherein each subsystem is configured to receive pairs of input signals, to multiply the pairs of input signals to produce product signals, to add the product signals to produce a corresponding first sum signal, and to add, in conjunction with a cycle of a clock signal, the corresponding first sum signal to an accumulated sum of previous corresponding first sum signals to produce a corresponding first output signal; and
first adders, wherein each first adder is coupled directly to a corresponding set of the subsystems and is configured to receive, from each of the subsystems in the corresponding set of the subsystems, the corresponding first sum signal and to produce a corresponding second sum signal.

2. The system of claim 1 , wherein each subsystem comprises:
a set of multipliers, wherein each multiplier of the set of multipliers is configured to receive a corresponding pair of the pairs of input signals and to produce a corresponding product signal;
a second adder configured to receive, from each multiplier of the set of multipliers, the corresponding product signal and to produce the corresponding first sum signal; and
a first accumulator configured to receive the corresponding first sum signal and to add, in conjunction with the cycle of the clock signal, the corresponding first sum signal to the accumulated sum of previous corresponding first sum signals to produce the corresponding first output signal.

3. The system of claim 2 , wherein each first adder is a pair of first adders and wherein, for each subsystem, the set of multipliers is a pair of sets of multipliers, the second adder is a pair of second adders, and the first accumulator is a pair of first accumulators.

4. The system of claim 3 , wherein a first adder of the pair of first adders is configured to operate in parallel with a second adder of the pair of first adders and wherein, for each subsystem, a first set of multipliers of the pair of sets of multipliers, a first adder of the pair of second adders, and a first accumulator of the pair of first accumulators are configured to operate in parallel with a second set of multipliers of the pair of sets of multipliers, a second adder of the pair of second adders, and a second accumulator of the pair of first accumulators.

5. The system of claim 3 , wherein each subsystem further comprises:
a bit shifter configured to receive the corresponding first sum signal of a first adder of the pair of second adders and to produce a corresponding bit-shifted first sum signal;
a third adder configured to receive the corresponding first sum signal of a second adder of the pair of second adders and the corresponding bit-shifted first sum signal and to produce a corresponding third sum signal; and
a multiplexer configured to receive the corresponding first sum signal of the second adder of the pair of second adders, the corresponding third sum signal, and a corresponding selector signal and to produce, dependent upon a value of the corresponding selector signal, one of the corresponding first sum signal of the second adder of the pair of second adders and the corresponding third sum signal;
wherein a first accumulator of the pair of first accumulators is configured to receive, dependent upon the value of the corresponding selector signal, one of the corresponding first sum signal of the second adder of the pair of second adders and the corresponding third sum signal.

6. The system of claim 3 , further comprising, for each set of the subsystems, a pair of second accumulators, wherein:
a first accumulator of the pair of second accumulators is coupled to a corresponding first adder of the pair of first adders and is configured to receive the corresponding second sum signal of the corresponding first adder of the pair of first adders and to add, in conjunction with the cycle of the clock signal, the corresponding second sum signal of the corresponding first adder of the pair of first adders to an accumulated sum of previous corresponding second sum signals of the corresponding first adder of the pair of first adders to produce a first output signal of a corresponding pair of second output signals; and
a second accumulator of the pair of second accumulators is coupled to a corresponding second adder of the pair of first adders and is configured to receive the corresponding second sum signal of the corresponding second adder of the pair of first adders and to add, in conjunction with the cycle of the clock signal, the corresponding second sum signal of the corresponding second adder of the pair of first adders to an accumulated sum of previous corresponding second sum signals of the corresponding second adder of the pair of first adders to produce a second output signal of the corresponding pair of second output signals.

7. The system of claim 6 , further comprising a pair of multiplexers, wherein, for each set of the subsystems, a first accumulator of the pair of first accumulators of a single subsystem is the first accumulator of the pair of second accumulators and a second accumulator of the pair of first accumulators of the single subsystem is the second accumulator of the pair of second accumulators, and wherein:
a first multiplexer of the pair of multiplexers is configured to receive the corresponding first sum signal of the first adder of the pair of second adders of the single subsystem, the corresponding second sum signal of the first adder of the pair of first adders, and a first selector signal and to produce, dependent upon a value of the first selector signal, one of the corresponding first sum signal of the first adder of the pair of second adders of the single subsystem and the corresponding second sum signal of the first adder of the pair of first adders;
the first accumulator of the pair of first accumulators of the single subsystem that is the first accumulator of the pair of second accumulators is configured to receive, dependent upon the value of the first selector signal, one of the corresponding first sum signal of the first adder of the pair of second adders of the single subsystem and the corresponding second sum signal of the first adder of the pair of first adders;
a second multiplexer of the pair of multiplexers is configured to receive the corresponding first sum signal of the second adder of the pair of second adders of the single subsystem, the corresponding second sum signal of the second adder of the pair of first adders, and a second selector signal and to produce, dependent upon a value of the second selector signal, one of the corresponding first sum signal of the second adder of the pair of second adders of the single subsystem and the corresponding second sum signal of the second adder of the pair of first adders; and
the second accumulator of the pair of first accumulators of the single subsystem that is the second accumulator of the pair of second accumulators is configured to receive, dependent upon the value of the second selector signal, one of the corresponding first sum signal of the second adder of the pair of second adders of the single subsystem and the corresponding second sum signal of the second adder of the pair of first adders.

8. The system of claim 6 , further comprising: a third adder coupled directly to each pair of first adders and configured to receive, from each pair of first adders, the corresponding second sum signal and to produce a third sum signal.

9. The system of clai

Assignees

• Intel Corp

Inventors

• Gupta Niraj
• N Karthik

Classifications

• G06F17/15 Primary

  Correlation function computation {including computation of convolution operations (arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00)} · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F17/10 Primary

  Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)} · CPC title