Method and device implementing execute-only memory protection

Patent metadata

Field	Value
Publication number	US-9489316-B2
Application number	US-201313842006-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.

First claim

What is claimed is:

1. A method comprising:
receiving a first read request for a first instruction stored at a first address of un-protected memory space, wherein accesses to unprotected memory are not selectively allow or prevent read requests based upon whether the read requests are operand requests;
receiving, at a memory controller, a second read request for a first operand stored at a second address of protected memory space, wherein protected memory space does selectively allow or prevent read requests based upon whether the read requests are operand requests; and
allowing, by the memory controller, the second read request in response to meeting at least one criteria selected from the group of criteria consisting of:
comparing the first address to the second address, and determining based upon the comparison that the second read request being within a predefined distance of the first address; and
receiving an indicator at the memory controller from a source of the second read request that a specific addressing mode was used to calculate the second address;
otherwise preventing the second read request, by the memory controller, in response to not meeting at least one of the criteria.

2. The method of claim 1 , wherein the at least one criteria is the second read request being within the predefined distance of the first address.

3. The method of claim 1 , wherein the at least one criteria is the receiving an indicator, and the source is a first data processor and the indicator is generated by the first data processor in response to executing an instruction needing an operand a within the predefined distance of a program counter of the first instruction, wherein a location of the operand relative the program counter is specified at an index field of the instruction.

4. The method of claim 2 , wherein the predefined distance is based upon a maximum PC-relative addressing offset supported by the first instruction.

5. The method of claim 2 , wherein the predefined distance is a fixed value.

6. The method of claim 2 , wherein the predefined distance is a programmable value.

7. The method of claim 2 further comprising:
providing the first instruction to the source in response to the first read request; and
wherein the first operand is an operand of the first instruction.

8. The method of claim 2 further comprising:
providing the first instruction to the source in response to the first read request; and
wherein the first operand is not an operand of the first instruction.

9. The method of claim 2 , wherein the first instruction is the instruction most recently fetched prior to receiving the second read request.

10. The method of claim 1 , wherein selectively allowing the second read request is in response to receiving the indicator from the source.

11. The method of claim 10 , wherein the specific operand addressing mode is program counter relative addressing mode.

12. A device comprising:
a first data processor;
a memory; and
a validation circuit coupled to the first data processor and to the memory,
in response to receiving an operand read requests from the first data processor at the validation circuit to access a first type of memory space, the validation circuit to selectively allow an operand read request to the first type of memory space in response to meeting at least one criteria selected from the group of criteria consisting of:
determining, in response to comparing an address of the operand read request to an address of a previously fetched instruction, that the operand read request is within a first predefined address distance of a previously fetched instruction; and
an indicator with the operand read request received at the validation circuit indicating that a specific addressing mode was used to calculate an address of the operand read request;

otherwise the validation circuit prevents the operand read request in response to at least one of the criteria not being met.

13. The device of claim 12 , wherein the at least one criteria is the operand read request being within the first predefined address distance of a previously fetched instruction.

14. The device of claim 12 , wherein the at least one criteria is in response to the indicator with the operand read request indicating that the specific addressing mode was used to calculate the address of the operand read request.

15. The device of claim 14 , wherein the specific addressing mode is PC-relative addressing mode.

16. A device comprising:
a first data processor, the first data processor comprising an output to generate an attribute indicator for operand read requests that indicates whether or not target addresses of the operand read requests were calculated using a specific type of addressing mode;
a memory; and
a validation circuit coupled to the first data processor and to the memory,
in response to receiving at the validation circuity a first read request and the attribute indicator from the first data processor to access a first type of memory space, the validation circuit to determine whether the first read request is an operand request or an instruction request, and
in response to the first read request being an operand request, the validation circuit to selectively allow the first read request in response to the attribute indicator indicating that a target address of the first read request was calculated using the specific type of addressing mode, and
in response to the first read request being an instruction request, the validation circuit to allow the first read to proceed without regards to an addressing mode used to calculate the target address of the first read request.

Assignees

• Circello Joseph C
• Mccarthy Daniel M
• Schimke David J
• Freescale Semiconductor Inc

Inventors

• Circello Joseph C
• Mccarthy Daniel M
• Schimke David J

Classifications

• G06F9/3814

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/34

  Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} · CPC title