Conditional page fault control for page residency

US9489313B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9489313-B2
Application numberUS-201314035643-A
CountryUS
Kind codeB2
Filing dateSep 24, 2013
Priority dateSep 24, 2013
Publication dateNov 8, 2016
Grant dateNov 8, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides for systems and methods to process a non-resident page that may include attempting to access the non-resident page, an address for the non-resident page pointing to a memory page containing default values, determining that the non-resident page should not cause a page fault based on an indicator indicating that a particular non-resident page should not generate a page fault, returning an indication that a memory read did not translate and returning the default value when the access of the non-resident page is a read and the non-resident page should not cause a page fault. Another example may discontinue a write when the access of the non-resident page is a write and the non-resident page should not cause a page fault.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of processing a non-resident page comprising: determining, with a memory management unit (MMU), that a processor attempted to access a first non-resident page, the first non-resident page comprising a page that does not map to a page in memory; reading a first set of one or more values indicative of whether a page fault is to occur from the access to the first non-resident page or whether the page fault is not to occur from the access to the first non-resident page based on whether the first non-resident page is for texture information or not for texture information, wherein the first set of one or more values indicates that the page fault is not to occur based on the first non-resident page being for texture information and indicates that the page fault is to occur based on the first non-resident page not being for texture information; in response to the determination that the processor attempted to access the first non-resident page, determining, with the MMU, whether the page fault is to occur from the access to the first non-resident page or whether the page fault is not to occur from the access to the first non-resident page based on the first set of one or more values; in response to the first non-resident page being for texture information and the determination that the page fault is not to occur from the access to the first non-resident page, returning, to the processor with the MMU: an indication that a memory read did not translate, and an address for default values when the access of the first non-resident page is a read; determining, with the MMU, that the processor attempted to access a second non-resident page, the second non-resident page comprising a page that does not map to a page in the memory; reading a second set of one or more values indicative of whether a page fault is to occur from the access to the second non-resident page or whether the page fault is not to occur from the access to the second non-resident page based on whether the second non-resident page is for texture information or not for texture information, wherein the second set of one or more values indicates that the page fault is not to occur based on the second non-resident page being for texture information and indicates that the page fault is to occur based on the second non-resident page not being for texture information; in response to the determination that the processor attempted to access the second non-resident page, determining, with the MMU, whether the page fault is to occur from the access to the second non-resident page or whether the page fault is not to occur from the access to the second non-resident page based on the second set of one or more values; and in response to the second non-resident page not being for texture information and the determination that the page fault is to occur from the access to the second non-resident page, receiving, with the processor, information indicative of the page fault of the second non-resident page. 2. The method of claim 1 , wherein reading the first set of one or more values comprises reading a bit or a flag, and wherein determining whether the page fault is to occur or is not to occur comprises determining whether the page fault is to occur or is not to occur based on the bit or flag. 3. The method of claim 1 , further comprising performing a residency check when the default values are returned. 4. The method of claim 1 , wherein the access comprises a read to a partially-resident texture. 5. The method of claim 4 , further comprising reading a coarseness level of the partially-resident texture as part of the access to the first non-resident page. 6. The method of claim 1 , wherein determining that the processor attempted to access comprises determining that the processor attempted to access the first non-resident page for color buffering. 7. A method of processing a non-resident page comprising: determining, with a memory management unit (MMU), that a processor attempted to access a first non-resident page, the first non-resident page comprising a page that does not map to a page in memory; reading a first set of one or more values indicative of whether a page fault is to occur from the access to the first non-resident page or whether the page fault is not to occur from the access to the first non-resident page based on whether the first non-resident page is for texture information or not for texture information, wherein the first set of one or more values indicates that the page fault is not to occur based on the first non-resident page being for texture information and indicates that the page fault is to occur based on the first non-resident page not being for texture information; in response to the determination that the processor attempted to access the first non-resident page, determining, with the MMU, whether the page fault is to occur from the access to the first non-resident page or whether the page fault is not to occur from the access to the first non-resident page based on the first set of one or more values; in response to the first non-resident page being for texture information and the determination that the page fault is not to occur from the access to the first non-resident page, discontinuing a write access of the first non-resident page by the processor; determining, with MMU, that the processor attempted to access a second non-resident page, the second non-resident page comprising a page that does not map to a page in the memory; reading a second set of one or more values indicative of whether a page fault is to occur from the access to the second non-resident page or whether the page fault is not to occur from the access to the second non-resident page based on whether the second non-resident page is for texture information or not for texture information, wherein the second set of one or more values indicates that the page fault is not to occur based on the second non-resident page being for texture information and indicates that the page fault is to occur based on the second non-resident page not being for texture information; in response to the determination that the processor attempted to access the second non-resident page, determining, with the MMU, whether the page fault is to occur from the access to the second non-resident page or whether the page fault is not to occur from the access to the second non-resident page based on the second set of one or more values; and in response to the second non-resident page not being for texture information and the determination that the page fault is to occur from the access to the second non-resident page, receiving, with the processor, information indicative of the page fault of the second non-resident page. 8. The method of claim 7 , wherein an address for the first non-resident page points to a memory page containing default values, the method further comprising comparing an address in a page table with an address value for the memory page containing default values, wherein determining that the processor attempted to access the first non-resident page comprises determining that the processor attempted to access the first non-resident page based on the comparison. 9. The method of claim 8 , wherein the address value for the memory page containing default values is stored in a register. 10. The method of claim 7 , wherein an address for the first non-resident page points to a memory page containing default values, wherein reading the one or more values comprises reading the default values, and wherein the default values indicate that a page is resident or non-resident. 11. The method of claim 7 , further comprising recalculating data lost from a disc

Assignees

Inventors

Classifications

  • In image processor or graphics adapter · CPC title

  • in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

  • Memory management · CPC title

  • using page tables, e.g. page table structures · CPC title

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Frequently asked questions

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What does patent US9489313B2 cover?
The present disclosure provides for systems and methods to process a non-resident page that may include attempting to access the non-resident page, an address for the non-resident page pointing to a memory page containing default values, determining that the non-resident page should not cause a page fault based on an indicator indicating that a particular non-resident page should not generate a…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/1009. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).