Cache line eviction based on write count

Patent metadata

Field	Value
Publication number	US-9489308-B2
Application number	US-201214387554-A
Country	US
Kind code	B2
Filing date	Apr 27, 2012
Priority date	Apr 27, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A method of shielding a memory device ( 110 ) from high write rates comprising receiving instructions to write data at a memory container ( 105 ), the memory controller ( 105 ) composing a cache ( 120 ) comprising a number of cache lines defining stored data, with the memory controller ( 105 ), updating a cache line in response to a write hit in the cache ( 120 ), and with the memory controller ( 105 ), executing the instruction to write data in response to a cache miss to a cache line within the cache ( 120 ) in which the memory controller ( 105 ) prioritizes for writing to the cache ( 120 ) over writing to the memory device ( 110 ).

First claim

What is claimed is:

1. A method comprising:
receiving instructions to write a data line at a memory controller, the memory controller comprising a cache comprising a number of cache lines defining stored data and associated write counters;
with the memory controller, in response to a cache hit, updating a corresponding cache line with the data line; and
with the memory controller, in response to a cache miss,
retrieving the associated write counter for the data line from a memory device,
writing a lowest write count data line to the memory device, lowest write count data line being selected from the data lines stored in the cache and the data line from the instructions,
incrementing the associated write counter of the lowest write count data line, and
if the lowest write count data line is not the data line from the instructions, writing the data line from the instructions to the cache line previously occupied by the least written to data line.

2. The method of claim 1 , in which the memory device is a memristive device.

3. The method of claim 1 , in which the cache implements a write-back policy.

4. The method of claim 1 , in which the memory device comprises a number of data lines separated into spare lines and initial lines and in which the method further comprises:
receiving instructions to write data to an initial line of memory in the memory device;
reading data defining a number of times data has been written to the initial line of memory; and
determining if a predetermined maximum threshold of write times has been exceeded for the initial line of memory.

5. The method of claim 4 , in which, if the maximum threshold of write times has not been exceeded for the initial line of memory:
updating a counter value associated with the initial line of memory incrementally; and
writing data to the initial line of memory.

6. The method of claim 4 , in which if the maximum threshold of write times has been exceeded for the initial line of memory:
selecting a spare line; and
storing an address of the spare peel line and a redirection flag into the initial line of memory.

7. The method of claim 1 , further comprising selecting the lowest write count data line by retrieving the write counts for each cache line from the cache and comparing the write counts retrieved from the cache and the write count retrieved from the memory device.

8. A system, comprising:
a memory controller;
a memory device communicatively coupled to the memory controller;
a write shielding cache communicatively coupled to the memory controller and memory device;
in which the memory controller is to:
receive a write request comprising a data line;

in response to a cache hit in the write shielding cache, update a cache line in the write shielding cache;
in response to a cache miss in the write shielding cache,
retrieve an associated write counter for the data line from the memory device,
select a lowest write count data line from the data lines stored in the cache and the data line from the request by comparing write counters of the data lines,
write the lowest write count data line to the memory device, and
if the lowest write count data line is not the data line from the request, writing the data line from the request to the cache line previously occupied by the least written to data line.

9. The system of claim 8 in which the memory controller is to write the lowest write count data line to the memory device by:
and
determining if the write counter for the lowest write count data line exceeds a predetermined maximum threshold.

10. The system of claim 9 , in which the memory controller is to:
if the write counter for the lowest write count data line does not exceed the maximum threshold:
update a counter value associated with the line of memory incrementally; and
write data to the memory line; and

if the write counter for the lowest write count data line does exceed the maximum threshold:
select a new line from a pool of spare lines in the memory device; and
store an address of the new line and a redirection flag at the initial line for lowest write count data line.

11. A method of shielding a memory device from high write rates comprising:
receiving instructions to write data at a memory controller, the memory controller comprising a cache comprising a number of cache lines defining stored data;
with the memory controller, updating a cache line in response to a write hit in the cache; and
with the memory controller, executing the instruction to write data in response to a cache miss to a cache line within the cache;
in which the memory controller prioritizes for writing to the cache over writing to the memory device,
in which the memory device comprises a number of data lines separated into spare lines and initial lines and in which the method further comprises:
receiving instructions to write data to an initial line of memory in the memory device;
reading data defining a number of times data has been written to the initial line of memory;
determining if a predetermined maximum threshold of write times has been exceeded for the initial line of memory;
in which if the maximum threshold of write times has been exceeded for the initial line of memory:
removing a line from a spare pool line in the memory; and
entering in an address of the spare pool line and a redirection flag into the line of memory.

Assignees

• Warner Craig
• Gostin Gary
• Pickett Matthew D
• Hewlett Packard Entpr Dev Lp

Inventors

• Warner Craig
• Gostin Gary
• Pickett Matthew D

Classifications

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F2212/312

  In storage controller · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F2212/69

  Physics · mapped topic