Multi domain bridge with auto snoop response

Patent metadata

Field	Value
Publication number	US-9489307-B2
Application number	US-201314031390-A
Country	US
Kind code	B2
Filing date	Sep 19, 2013
Priority date	Oct 24, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The powerdown mechanism is isolated to just the asynchronous bridge implemented between the master and the interconnect with a basic request/acknowledge handshake between the master subsystem and the asynchronous bridge.

First claim

What is claimed is:

1. An asynchronous bridge operable to connect a plurality of clock and powerdown domains, consisting of:
a slave interface operable within a slave clock and powerdown domain;
a master interface operable within a master clock and powerdown domain;
an asynchronous crossing connected to said slave interface and said master interface;
wherein upon detecting a powerdown request from a master device connected to said master interface said asynchronous bridge is operable to
stop accepting snoop transactions from a slave device connected to said slave interface,
automatically responding to in-flight snoop transactions by internally score boarding said in-flight snoop transactions,
following automatically responding to all said in-flight snoop transactions, transmitting a powerdown acknowledge signal to the connected master device and powering down said master interface, and
following transmitting said powerdown acknowledge signal, automatically responding to snoop requests with a “normal—no data” snoop response while said master interface is in a powerdown mode.

2. The asynchronous bridge of claim 1 wherein:
the slave interface is operable to remain active while the master interface is powered down.

3. The asynchronous bridge of claim 1 wherein:
the automatically responding to snoop requests with a “normal—no data” snoop response terminates upon detection by the asynchronous bridge that the master interface has powered up and came out of the reset state.

4. The asynchronous bridge of claim 1 wherein:
the asynchronous bridge automatically responding to snoop requests with a “normal—no data” snoop response upon system power up with the master held in reset.

Assignees

• Texas Instruments Inc

Inventors

• Wu Daniel B
• Anderson Timothy D

Classifications

• G06F2212/6042

  Allocation of cache space to multiple users or processors · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F13/4013

  with data re-ordering, e.g. Endian conversion · CPC title