Delivery of events from a virtual machine to a thread executable by multiple host CPUs using memory monitoring instructions

Patent metadata

Field	Value
Publication number	US-9489228-B2
Application number	US-201213686442-A
Country	US
Kind code	B2
Filing date	Nov 27, 2012
Priority date	Nov 27, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A method and system for managing a virtual computing system including a hypervisor managing a virtual machine (VM) configured to communicate with a thread executable by multiple host central processing units (CPUs), using memory monitoring instructions. The hypervisor provides the virtual machine with a first notification identifying a first designated memory range writeable by a virtual central processing unit (VCPU) associated with the virtual machine and a first instruction to write to the first designated memory range to communicate with the thread running on a first host CPU. The hypervisor further identifies movement of the thread from the first host CPU to a second host CPU and provides to the virtual machine a second notification identifying a second designated memory range and a second instruction to write to the second designated memory range to communicate with the thread running on the second host CPU.

First claim

What is claimed is:

1. A method comprising:
providing, by a processing device executing a hypervisor to a virtual machine executing a guest, a first notification identifying a first designated memory range writeable by a virtual central processing unit (VCPU) associated with the virtual machine to communicate with a thread running on a first host central processing unit (CPU);
providing, by the hypervisor to the VCPU, a first instruction to write to the first designated memory range to communicate with the thread;
identifying movement of the thread from running on the first host CPU to running on a second host CPU;
providing in response to identifying movement of the thread from running on the first host CPU to running on the second host CPU, by the hypervisor to the virtual machine, a second notification identifying a second designated memory range writeable by the VCPU to communicate with the thread running on the second host CPU;
providing, by the hypervisor to the VCPU, a second notification to write to the second designated memory range to communicate with the thread;
executing, by the second host CPU running the thread, a memory monitoring instruction to identify the second designated memory range; and
writing, by the VCPU, data identifying an event for execution by the thread to the second designated memory range, without causing an exit to the hypervisor.

2. The method of claim 1 , wherein the thread is executable by a plurality of host CPUs comprising the first host CPU and the second host CPU.

3. The method of claim 2 , wherein the hypervisor maintains an association between each of the plurality of host CPUs and a corresponding designated memory range of a shared memory.

4. The method of claim 1 , further comprising:
detecting, by the hypervisor, that the thread stopped executing on at least one of the first host CPU or the second host CPU;
instructing the VCPU of the virtual machine to stop writing to at least one of the first designated memory range or the second designated memory range, causing an exit to the hypervisor; and
performing, by the hypervisor, a wake-up of the thread.

5. The method of claim 1 , further comprising maintaining, by the virtual machine, a first association between the first designated memory range and the first host CPU and a second association between the second designated memory range and the second host CPU.

6. The method of claim 1 , wherein the first host CPU executes a memory monitoring instruction on the first designated memory range.

7. A non-transitory computer readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
provide, by the processing device executing a hypervisor to a virtual machine executing a guest, a notification identifying a first designated memory range writeable by a virtual central processing unit (VCPU) associated with the virtual machine to communicate with a thread running on a first host central processing unit (CPU);
providing, by the hypervisor to the VCPU, an instruction to write to the identified address range to communicate with the thread;
identifying movement of the thread from running on the first host CPU to running on a second host CPU;
modify in response to identifying movement of the thread from running on the first host CPU to running on the second host CPU, by the hypervisor, a mapping of an address associated with the virtual machine to map to a second designated memory range associated with the second host CPU;
execute, by the second host CPU running the thread, a memory monitoring instruction to identify the second designated memory range; and
write, by the VCPU, data identifying an event for execution by the thread to the second designated memory range, without causing an exit to the hypervisor.

8. The non-transitory computer readable storage medium of claim 7 , wherein the thread is executable by a plurality of host CPUs comprising the first host CPU and the second host CPU.

9. The non-transitory computer readable storage medium of claim 8 , the processing device to:
detect, by the hypervisor, that the thread stopped executing on at least one of the plurality of host CPUs;
perform, by the hypervisor, a write-protect operation on a designated memory range associated with the at least one of the plurality of host CPUs;
perform an exit to the hypervisor resulting from an attempt by the VCPU of the virtual machine to write to the write-protected designated memory block; and
perform, by the hypervisor, a wake-up of the thread.

10. The non-transitory computer readable storage medium of claim 7 , wherein the first host CPU executes a memory monitoring instruction on the first designated memory range.

11. The non-transitory computer readable storage medium of claim 7 , wherein the write to the second designated memory range comprises executing an atomic instruction.

12. A computer system comprising:
a memory; and
a processing device operatively coupled to the memory, the processing device to execute a hypervisor having access to a plurality of host central processing units (CPUs) comprising a first host CPU and a second host CPU, the processing device to:
provide a virtual machine executing a guest, a first notification identifying a first designated memory range writeable by a VCPU associated with the virtual machine to communicate with a thread running on the first host CPU;
provide to the VCPU, a first instruction to write to the identified address range to communicate with the thread;
identify movement of the thread from running on the first host CPU to running on a second host CPU;
provide to the virtual machine in response to identifying movement of the thread from running on the first host CPU to running on the second host CPU, a second notification identifying a second designated memory range writeable by the VCPU to communicate with the thread running on the second host CPU; and
provide to the VCPU, a second instruction to write to the second designated memory range to communicate with the thread;
execute, by the second host CPU running the thread, a memory monitoring instruction to identify the second designated memory range; and
write, by the VCPU, data identifying an event for execution by the thread to the second designated memory range, without causing an exit to the hypervisor.

13. The computer system of claim 12 , the hypervisor to maintain an association between each of the plurality of host CPUs and a corresponding designated memory range of a shared memory.

14. The computer system of claim 12 , the hypervisor to:
detect that the thread stopped executing on at least one of the first host CPU or the second host CPU,
instruct the VCPU of the virtual machine to stop writing to at least one of the first designated memory range or the second designated memory range, causing an exit to the hypervisor, and
perform a wake-up of the thread.

15. The computer system of claim 12 , the hypervisor to maintain a first association between the first designated memory range and the first host CPU and a second association between the second designated memory range and the second host CPU.

16. The computer system of claim 12 , wherein the first host CPU executes a memory monitoring instruction on the first designated memory range.

17. The computer system of claim 12 , the hypervisor to:
detect that the thread stopped executing on at least one of the plurality of host CPUs;
perform a write-protect operation on a designated memory range associated with the at least one of the plurality of hos

Assignees

• Red Hat Israel Ltd

Inventors

• Tsirkin Michael
• Kivity Avi
• Laor Dor

Classifications

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title