Systems and methods for reducing power consumption of a communication device

Patent metadata

Field	Value
Publication number	US-9489033-B2
Application number	US-201414461635-A
Country	US
Kind code	B2
Filing date	Aug 18, 2014
Priority date	Nov 7, 2007
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Generally, this disclosure describes an energy-efficient Ethernet communications approach including use of clock gating of transmit circuitry.

First claim

What is claimed is:

1. A system comprising:
circuitry, comprising an Ethernet MAC (Media Access Control), capable, when operational, to:
cause generation of a signal indicating a lower power idle power state, the lower power idle power state comprising a lower power state than an active power state;
cause generation of a wake signal for a first Ethernet link partner;
after a predefined period of time, cause transmission of at least one Ethernet data frame to the first Ethernet link partner;
the circuitry, capable, when operational, to reduce power consumed by transmit circuitry in the lower power idle state, the circuitry to reduce power consumed by the transmit circuitry to control clock gating of a clock signal of the transmit circuitry.

2. The system of claim 1 , wherein the circuitry comprises a PHY.

3. The system of claim 2 , wherein the PHY comprises at least one of the following: a 10GBASE-T PHY and a 1000BASE-T PHY.

4. The system of claim 1 , wherein the circuitry comprises circuitry capable, when operational, to reduce power consumed by the PHY when in the lower power idle state.

5. The system of claim 4 , wherein the circuitry capable, when operational, to reduce power consumed by the PHY comprises circuitry to clock gate a clock signal of the PH0059.

6. The system of claim 1 , wherein the circuitry comprises circuitry of an Ethernet controller.

7. The system of claim 1 , further comprising:
a host processor; and
memory external to the host processor.

8. The system of claim 1 , wherein the circuitry comprises circuitry capable, when operational, to cause transfer of Ethernet data frames at a data rate negotiated with the first Ethernet link partner.

9. The system of claim 1 , wherein the circuitry comprises circuitry capable, when operational, to clock gate a clock signal of the Ethernet MAC.

10. The system of claim 1 , wherein the circuitry comprises circuitry capable, when operational, to clock gate an encoder.

11. The system of claim 1 , wherein the circuitry does not transmit an Ethernet data frame to the first Ethernet link partner when in the lower power idle state.

12. The system of claim 1 , wherein the circuitry comprises circuitry, when operational, to determine when to initiate the lower power idle state based on an amount available in a data buffer.

13. The system of claim 1 , wherein the circuitry comprises circuitry capable, when operational, to:
receive a wake signal from the first Ethernet link partner; and
receive at least one Ethernet data frame from the first Ethernet link partner.

14. The system of claim 13 , wherein the circuitry comprises circuitry capable, when operational, to reduce power consumed by receive circuitry.

15. The system of claim 14 , wherein the circuitry comprises circuitry capable, when operational, to clock gate a decoder.

16. The system of claim 14 , wherein the circuitry comprises circuitry capable, when operational, to clock gate Rx circuitry of a PHY.

17. The system of claim 1 , wherein the circuitry comprises circuitry capable, when operational, to clock gate at least one element of a transmit path and at least one element of a receive path.

18. The system of claim 17 , wherein the circuitry capable, when operational, to clock gate at least one element of a transmit path and at least one element of a receive path comprises circuitry to clock gate the at least one element of the transmit path independently of circuitry to clock gate the at least one element of the receive path.

19. The system of claim 1 , further comprising an SGMII.

20. An article comprising a non-transitory storage medium having stored thereon instructions that when executed enable circuitry to be capable to:
cause generation of a signal indicating a lower power idle power state, the lower power idle power state comprising a lower power state than an active power state;
cause generation of a wake signal for a first Ethernet link partner;
after a predefined period of time, cause transmission of at least one Ethernet data frame to the first Ethernet link partner;
wherein the instructions that when executed enable circuitry to be capable to reduce power consumed by transmit circuitry in the lower power idle state comprise instructions that when executed enable circuitry to be capable to control clock gating of a clock signal of the transmit circuitry.

21. The article of claim 20 , wherein the instructions comprise instructions that when executed enable circuitry to be capable to reduce power consumed by a PHY when in the lower power idle state.

22. The article of claim 21 , wherein the instructions comprise instructions that when executed enable circuitry to be capable to reduce power consumed by the PHY comprise instructions that when executed enable circuitry to be capable to clock gate a clock signal of the PHY.

23. The article of claim 20 , wherein the instructions comprise instructions that when executed enable circuitry to be capable to clock gate a clock signal of the Ethernet MAC.

24. The article of claim 20 , wherein the instructions comprise instructions that when executed enable circuitry to be capable to clock gate an encoder.

25. The article of claim 20 , wherein the instructions comprise instructions that when executed enable circuitry to:
receive a wake signal from the first Ethernet link partner; and
receive at least one Ethernet data frame from the first Ethernet link partner.

26. The article of claim 20 , wherein the instructions comprise instructions that when executed enable circuitry to reduce power consumed by receive circuitry.

27. The article of claim 20 , wherein the instructions comprise instructions that when executed enable circuitry to clock gate a decoder.

28. The article of claim 20 , wherein the instructions comprise instructions that when executed enable circuitry to clock gate Rx circuitry of a PHY.

29. The article of claim 20 , wherein the instructions comprise instructions that when executed enable circuitry to clock gate at least one element of a transmit path and at least one element of a receive path.

30. The article of claim 29 , wherein the instructions comprise instructions that when executed enable circuitry to clock gate the at least one element of the transmit path independently of circuitry to clock gate the at least one element of the receive path.

31. The article of claim 20 , wherein the instructions comprise instructions that when executed enable circuitry to determine when to initiate the lower power idle state based on an amount available in a data buffer.

Assignees

• Intel Corp

Inventors

• Hays Robert

Classifications

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• H04L12/10 Primary

  Current supply arrangements · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title