Method for fabricating silicon photonic waveguides

Patent metadata

Field	Value
Publication number	US-9488776-B2
Application number	US-201213543999-A
Country	US
Kind code	B2
Filing date	Jul 9, 2012
Priority date	Jul 9, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A method for fabricating electronic and photonic devices on a semiconductor substrate using complementary-metal oxide semiconductor (CMOS) technology is disclosed. A substrate is initially patterned to form a first region for accommodating electronic devices and a second region for accommodating photonic devices. The substrate within the first region is thicker than the substrate within the second region. Next, an oxide layer is formed on the substrate. The oxide layer within the first region is thinner than the oxide layer within the second region. A donor wafer is subsequently placed on top of the oxide layer. The donor substrate includes a bulk silicon substrate, a sacrificial layer and a silicon layer. Finally, the bulk silicon substrate and the sacrificial layer are removed from the silicon layer such that the silicon layer remains on the oxide layer.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate having a first region for accommodating electronic devices and a second region for accommodating photonic devices, wherein said first region is directly adjacent to said second region, wherein said substrate within said first region is thicker than said substrate within said second region;
an oxide layer located directly on said substrate within said first and second regions, wherein said oxide layer within said first region is thinner than said oxide layer within said second region; and
a silicon layer located directly on said oxide layer within said first and second regions.

2. The integrated circuit of claim 1 , wherein said substrate within said first region is epitaxially grown from said substrate.

3. The integrated circuit of claim 1 , wherein an electronic device is fabricated on said first region and a photonic device is fabricated on said second region.

4. The integrated circuit of claim 1 , wherein one of said electronic devices is a transistor.

5. The integrated circuit of claim 1 , wherein one of said photonic devices is a waveguide, a modulator or a demodulator.

Assignees

• Hill Craig M
• Pomerene Andrew T S
• Bae Sys Inf & Elect Sys Integ

Inventors

• Hill Craig M
• Pomerene Andrew T S

Classifications

• G02B6/136

  by etching · CPC title

• G02B6/132

  by deposition of thin films · CPC title

• G02B6/12004

  Combinations of two or more optical elements · CPC title

• G02B6/12 Primary

  of the integrated circuit kind (electric integrated circuits H10B, H10D84/00 - H10D89/00, H10F19/00, H10F39/00, H10H29/00, H10K19/00, H10K39/00, H10K59/00, H10N19/00, H10N39/00, H10N59/00, H10N69/00, H10N79/00, H10N89/00) · CPC title

• H10D84/40 Primary

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs · CPC title