Mode based skew to reduce scan instantaneous voltage drop and peak currents

Patent metadata

Field	Value
Publication number	US-9488692-B2
Application number	US-201414468394-A
Country	US
Kind code	B2
Filing date	Aug 26, 2014
Priority date	Aug 26, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.

First claim

What is claimed is:

1. An integrated circuit comprising:
a plurality of functional circuit blocks each coupled to receive a respective one of one or more clock signals, wherein each of the plurality of functional circuit blocks includes logic circuitry intended to perform a function of the integrated circuit;
a first plurality of clock-gating circuits, wherein each of the plurality of functional circuit blocks includes a subset comprising two or more clock-gating circuits each c…

Assignees

• Apple Inc

Inventors

• Bawa Asad A
• Marrou Benjamin A
• Ng Christopher
• Seningen Michael R
• Sabnis Mihir S
• Mohammed Zameeruddin
• Zhao Yi

Classifications

• G01R31/318552 Primary

  Physics · mapped topic

• G01R31/318563

  Physics · mapped topic

• G01R31/3177

  Physics · mapped topic

• G01R31/318575

  Physics · mapped topic

• G01R31/318541

  Physics · mapped topic