Residual material detection in backdrilled stubs

US9488690B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9488690-B2
Application numberUS-201414462628-A
CountryUS
Kind codeB2
Filing dateAug 19, 2014
Priority dateMay 20, 2014
Publication dateNov 8, 2016
Grant dateNov 8, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A stub of a via formed in a printed circuit board is backdrilled to a predetermined depth. A capacitance probe is positioned within the via. Then the capacitance probe is used to obtain a test capacitance measurement. The test capacitance measurement is compared to a predetermined baseline capacitance measurement. Residual conductive plating material in the backdrilled stub causes the test capacitance measurement to exceed the predetermined baseline capacitance measurement. An indication is made that the predetermined baseline capacitance measurement has been exceeded.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for measuring and assessing the adequacy of a backdrilling operation, the method comprising: backdrilling a stub of a via formed in a printed circuit board to a predetermined depth; positioning a capacitance probe within the via; subsequent to the backdrilling to the predetermined depth and the positioning the capacitance probe, using the capacitance probe to obtain a test capacitance measurement; comparing the test capacitance measurement to a predetermined baseline capacitance measurement, residual conductive plating material in the backdrilled stub causing the test capacitance measurement to exceed the predetermined baseline capacitance measurement; and indicating that the test capacitance measurement exceeds the predetermined baseline capacitance measurement. 2. The method of claim 1 , wherein the backdrilling is performed by a drilling device of a printed circuit board manufacturing machine, and wherein the positioning the capacitance probe is performed by a probe deployment device of the printed circuit board manufacturing machine. 3. The method of claim 2 , wherein the drilling device comprises a drill bit. 4. The method of claim 3 , wherein the probe deployment device comprises the drilling device, and wherein the capacitance probe comprises the drill bit. 5. The method of claim 3 , wherein the drill bit is hollow, and wherein the positioning of the capacitance probe further comprises moving the capacitance probe through an end of the drill bit. 6. The method of claim 2 , further comprising: backdrilling, using a second drilling device of the printed circuit board manufacturing machine, a second stub of a second via formed in a second printed circuit board to a second predetermined depth, the backdrilling of the second stub occurring substantially simultaneously with the backdrilling of the stub; positioning, using a second probe deployment device of the printed circuit board manufacturing machine, a second capacitance probe within the second via, the positioning of the second capacitance probe occurring substantially simultaneously with the positioning of the capacitance probe; using the second capacitance probe to obtain a second test capacitance measurement; comparing the second test capacitance measurement to a second predetermined baseline capacitance measurement, the second test capacitance measurement not exceeding the second predetermined baseline capacitance measurement; and indicating that the second test capacitance measurement does not exceed the second predetermined baseline capacitance measurement. 7. The method of claim 1 , wherein the comparing the test capacitance measurement to the baseline capacitance measurement is performed by a computer operatively coupled to the capacitance probe. 8. The method of claim 1 , wherein the conductive plating material comprises Copper. 9. The method of claim 1 , further comprising: re-drilling the stub. 10. The method of claim 1 , further comprising: adjusting the predetermined baseline capacitance measurement based on the sensitivity of an interface with which the via is intended to be associated.

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Classifications

  • Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00}) · CPC title

  • Acoustic transducer · CPC title

  • Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title

  • Measuring capacitance (capacitive sensors G01D5/24) · CPC title

  • related to vias or transitions between vias and transmission lines · CPC title

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What does patent US9488690B2 cover?
A stub of a via formed in a printed circuit board is backdrilled to a predetermined depth. A capacitance probe is positioned within the via. Then the capacitance probe is used to obtain a test capacitance measurement. The test capacitance measurement is compared to a predetermined baseline capacitance measurement. Residual conductive plating material in the backdrilled stub causes the test capa…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G01R31/2801. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).