Dynamically reconfigurable channelizer

Patent metadata

Field	Value
Publication number	US-9485125-B2
Application number	US-201414305685-A
Country	US
Kind code	B2
Filing date	Jun 16, 2014
Priority date	Jun 16, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

Embodiments are directed to a channelizer architecture configured to provide fully configurable frequency spectrum shaping by: establishing a plurality of parameters of the architecture, receiving an input signal, processing, by the architecture, the input signal in accordance with the plurality of parameters to obtain an output signal, analyzing the output signal to detect an object, and modifying the plurality of parameters to account for at least one dynamic condition associated with the object.

First claim

What is claimed is:

1. A method used by a channelizer architecture to provide fully configurable frequency spectrum shaping, the method comprising:
establishing a plurality of parameters of the architecture;
receiving an input signal;
processing, by the architecture, the input signal in accordance with the plurality of parameters to obtain an output signal;
analyzing the output signal to detect an object; and
simultaneously modifying the plurality of parameters to account for at least one dynamic condition associated with the object,
wherein the processing of the input signal further comprises down-converting the selected one or more outputs of the one or more up-converters to down-convert to an original clock domain.

2. The method of claim 1 , further comprising:
sampling the received input signal;
wherein processing the input signal comprises processing the sampled signal.

3. The method of claim 1 , wherein the plurality of parameters comprise a specification of at least one of: a channel width, a center frequency, a number of channels, and a latency.

4. The method of claim 1 , wherein the at least one dynamic condition comprises a change of the condition in terms of at least one of: modulation scheme, bandwidth, frequency, and amplitude.

5. The method of claim 1 , wherein the processing of the input signal comprises an application of a poly-phase filter to the input signal and application of a fast Fourier transform algorithm to an output of the poly-phase filter.

6. The method of claim 5 , wherein the processing of the input signal further comprises an application of one or more up-converters to an output of the fast Fourier transform algorithm to up-convert to a common clock domain.

7. The method of claim 6 , wherein the processing of the input signal further comprises selecting one or more outputs of the one or more up-converters.

8. The method of claim 1 , wherein the plurality of parameters is established as part of a mission planning phase.

9. The method of claim 1 , wherein the plurality of parameters is modified in accordance with a control program.

10. An apparatus comprising:
memory having instructions stored thereon that, when executed, cause the apparatus to:
establish a plurality of parameters of the apparatus;
receive an input signal;
process the input signal in accordance with the plurality of parameters to obtain an output signal;
analyze the output signal to detect an object; and
simultaneously modify the plurality of parameters to account for at least one dynamic condition associated with the object;

a poly-phase filter configured to split the input signal into a number of sub-bands,
wherein the instructions, when executed, cause the apparatus to:
apply a fast Fourier transform algorithm to an output of the poly-phase filter;

one or more up-converters coupled to an output of the fast Fourier transform algorithm, wherein the instructions, when executed, cause the apparatus to:
provide an up-conversion to a common clock domain using the one or more up-converters; and

a down-converter, wherein the instructions, when executed, cause the apparatus to:
down-convert the selected one or more outputs of the one or more up-converters to down-convert to an original clock domain.

11. The apparatus of claim 10 , wherein the instructions, when executed, cause the apparatus to:
sample the received input signal,
wherein processing the input signal comprises processing the sampled signal.

12. The apparatus of claim 10 , wherein the plurality of parameters comprises a specification of at least one of: a channel width, a center frequency, a number of channels, and a latency.

13. The apparatus of claim 10 , wherein the at least one dynamic condition comprises a change of the condition in terms of at least one of: modulation scheme, bandwidth, frequency, and amplitude.

14. The apparatus of claim 10 , further comprising:
one or more multiplexers, and
wherein the instructions, when executed, cause the apparatus to:
select one or more outputs of the one or more up-converters using the one or more multiplexers.

15. The apparatus of claim 10 , wherein the plurality of parameters is modified in accordance with a control program.

16. The apparatus of claim 10 , wherein the plurality of parameters is configured to be modified substantially in real-time and on a pulse-to-pulse basis, and wherein the apparatus is associated with at least one of a programmable logic device and a field programmable gate array.

Assignees

• Raytheon Co

Inventors

• Thompson Daniel
• Marr Harry B
• Okafor Nnaemeka
• Mclean Chris
• Romulo Aaron
• Molina Edwin

Classifications

• H04L27/00 Primary

  Modulated-carrier systems · CPC title

• H04B1/0035

  Channel filtering, i.e. selecting a frequency channel within a software radio system (multiplexing of multicarrier modulation signals being represented by different frequencies H04L5/06; multiplexing of multicarrier modulation signals H04L5/023) · CPC title

• H04J3/1694

  Allocation of channels in TDM/TDMA networks, e.g. distributed multiplexers (Passive Optical Networks H04Q11/0062) · CPC title

• H04L27/2652

  with polyphase implementation · CPC title

• H04J3/02

  Details (electronic switching or gating H03K17/00) · CPC title