Linearity of phase interpolators by combining current coding and size coding

Patent metadata

Field	Value
Publication number	US-9485084-B2
Application number	US-201414300127-A
Country	US
Kind code	B2
Filing date	Jun 9, 2014
Priority date	Jun 9, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.

First claim

What is claimed is:

1. A phase interpolator, comprising:
a pair of load resistors coupled to a supply voltage;
a first portion including a first plurality of branches, a plurality of tail current sources, and a plurality of source nodes, each branch of the first plurality of branches including a differential pair of transistors and a different one of the tail current sources of the plurality of tail current sources, wherein source terminals of differential pairs of transistors connect to form the plurality of source nodes,
wherein each tail current source of the plurality of tail current sources couples to one of the plurality of source nodes, and
wherein the differential pair of transistors and the plurality of tail current sources are configured in a current coding scheme;
a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme,
wherein each switch of the plurality of switches is coupled to and used to turn on or off a corresponding differential pair of transistors of the second plurality of differential pairs of transistors,
wherein the second plurality of differential pairs of transistors in said each branch of the second plurality of branches receives differential input signals with a particular phase that results from equally dividing 360 degrees by a total number of the second plurality of branches, and
wherein switches in two adjacent branches of the second plurality of branches are turned on to produce differential output signals having a desired phase between particular phases of the two adjacent branches;
wherein the first portion and the second portion are coupled to each other and to the pair of load resistors.

2. The phase interpolator of claim 1 , wherein a total number of switches turned on at any one time in all of the second plurality of branches is equal to the total number of switches in a single branch of the second plurality of branches.

3. The phase interpolator of claim 1 , wherein a number of the plurality of switches turned on in each of the two adjacent branches is proportional to how close the desired phase is to any one of the particular phases of the two adjacent branches.

4. The phase interpolator of claim 1 , further comprising
a plurality of coupling capacitors, each coupling capacitor coupled between source nodes in two adjacent branches of the first plurality of branches.

5. The phase interpolator of claim 1 , wherein the first portion and the second portion are coupled to each other and to the pair of load resistors at drain terminals of differential pairs of transistors in the first plurality of branches and drain terminals of the differential pairs of transistors in the second plurality of branches.

6. A method for improving linearity of a phase interpolator by combining a current coding scheme and a size coding scheme, comprising:
receiving a plurality of differential input signals at a corresponding plurality of branches, the corresponding plurality of branches comprising a first portion configured in the current coding scheme and a second portion configured in the size coding scheme, and each differential input signal having an assigned phase,
each branch of the first portion:
comprising a differential pair of source-coupled transistors, wherein source terminals of the differential pair of source-coupled transistors are connected to form a source node;
interpolating between assigned phases of the plurality of differential input signals by controlling an amount of current flowing through the source node of said each branch;
each branch of the second portion:
comprising a plurality of differential pairs of transistors and a plurality of switches;
interpolating between the assigned phases of the plurality of differential input signals by controlling a number of the plurality of differential pairs of transistors turned on by the plurality of switches, which comprises turning on or off a differential pair of transistor in the second portion using a corresponding switch of the plurality of switches coupled to the differential pair of transistors in the second portion,
wherein the assigned phase of each differential input signal in each of the first portion and the second portion is assigned by equally dividing 360 degree by a total number of the plurality of branches in each of the first portion and the second portion,
wherein for the plurality of branches of the first portion, the unit current sources are switched in two adjacent branches to produce a pair of differential output signals having a desired phase between the assigned phases of the two adjacent branches,
wherein for the plurality of branches of the second portion, the plurality of switches of two adjacent branches are turned on to produce a pair of differential output signals having a desired phase between the assigned phases of the two adjacent branches; and
coupling the first portion to the second portion.

7. The method of claim 6 , a total number of switches turned on at any one time in all of the plurality of branches in the second portion is equal to the total number of switches in a single branch of the second portion.

8. The method of claim 6 , wherein a number of the plurality of switches turned on in each of the two adjacent branches in the second portion is proportional to how close the desired phase is to any one of the particular phases of the two adjacent branches.

9. The method of claim 6 , further comprising
coupling capacitance between the source nodes of a pair of adjacent branches in the first portion.

10. An apparatus for improving linearity of a phase interpolator by combining a current coding scheme and a size coding scheme, the apparatus comprising:
means for receiving a plurality of differential input signals at a corresponding plurality of branches, the corresponding plurality of branches comprising a first portion configured in the current coding scheme and a second portion configured in the size coding scheme, and each differential input signal having an assigned phase,
each branch of the first portion:
comprising a differential pair of source-coupled transistors, wherein source terminals of the differential pair of source-coupled transistors are connected to form a source node;
means for interpolating between assigned phases of the plurality of differential input signals by controlling an amount of current flowing through the source node of said each branch;
each branch of the second portion:
comprising a plurality of differential pairs of transistors and a plurality of switches;
means for interpolating between the assigned phases of the plurality of differential input signals by controlling a number of the plurality of differential pairs of transistors turned on by the corresponding plurality of switches, which comprises means for turning on or off a differential pair of transistors in the second portion using a corresponding switch of the plurality of switches coupled to the differential pair of transistors in the second portion,
wherein the assigned phase of each differential input signal in each of the first portion and the second portion is assigned by equally dividing 360 degrees by a total number of the plurality of branches in each of the first portion and the second portion,
wherein for the plurality of branches of the first portion, the unit current sources are switched in two adjacent branches to produce a pair of differential output signals having a desired phase between the assigned phases of the two adja

Assignees

• Qualcomm Inc

Inventors

• Sun Li
• Zhu Zhi
• Kong Xiaohua
• Arcudia Kenneth Luis
• Chen Zhiqin

Classifications

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K2005/00065

  by current control, e.g. by parallel current control transistors · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title