Apparatus for compensating for skew between data signals and clock signal

Patent metadata

Field	Value
Publication number	US-9485081-B2
Application number	US-201414207447-A
Country	US
Kind code	B2
Filing date	Mar 12, 2014
Priority date	Mar 14, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

An apparatus for compensating for a skew is provided between data signals supplied through a plurality of data lines and a clock signal supplied through a clock line. A skew compensation apparatus includes a plurality of data receivers each configured to delay a data signal supplied through a corresponding data line based on associated phase difference data and to output the delayed data signal, a clock receiver configured to receive a clock signal supplied through a clock line, and a phase controller configured to select any one of the plurality of data receivers and to output, to the selected data receiver, a phase control signal configured to correct the phase difference data of the selected data receiver based on the phase difference between a data signal output from the selected data receiver and the clock signal.

First claim

What is claimed is:

1. A skew compensation apparatus, comprising:
a plurality of data receivers each configured to delay a data signal supplied through a corresponding data line based on associated phase difference data and to output a delayed data signal of a plurality of delayed data signals;
a clock receiver configured to receive a clock signal supplied through a clock line; and
a phase controller configured to select one of the plurality of data receivers and to output, to the selected data receiver, a phase control signal configured to correct phase difference data of the selected data receiver based on a phase difference between a corresponding delayed data signal output from the selected data receiver and the clock signal, the phase controller comprising a multiplexer configured to output the corresponding delayed data signal output from the selected data receiver, the corresponding delayed data signal being selected from among the plurality of delayed data signals output from the plurality of data receivers.

2. The skew compensation apparatus of claim 1 , wherein the phase controller is configured to correct corresponding phase difference data of each of the plurality of data receivers by sequentially selecting the plurality of data receivers.

3. The skew compensation apparatus of claim 1 , wherein each of the plurality of data receivers comprises:
a finite state machine configured to correct and store the phase difference data in response to the phase control signal; and
a delay circuit configured to delay the data signal supplied through the corresponding data line, based on the phase difference data stored in the finite state machine, and to output the delayed data signal.

4. The skew compensation apparatus of claim 1 , wherein the clock receiver is configured to delay the clock signal supplied through the clock line for a certain time and to output a delayed clock signal.

5. The skew compensation apparatus of claim 1 , wherein the phase controller is configured to output the phase control signal so that the phase difference between a clock signal output from the clock receiver and the corresponding delayed data signal output from the selected data receiver becomes 90 degrees.

6. A skew compensation apparatus, comprising:
a plurality of data receivers each configured to delay a data signal supplied through a corresponding data line based on associated phase difference data and to output a delayed data signal of a plurality of delayed data signals;
a clock receiver configured to receive a clock signal supplied through a clock line; and
a phase controller configured to select one of the plurality of data receivers and to output, to the selected data receiver, a phase control signal configured to correct phase difference data of the selected data receiver based on a phase difference between a corresponding delayed data signal output from the selected data receiver and the clock signal,
wherein the phase controller comprises:
a multiplexer configured to output the corresponding delayed data signal output from the selected data receiver, selected from among the plurality of delayed data signals output from the plurality of data receivers, in response to a selection signal;
a phase control circuit configured to output the phase control signal based on the phase difference between the clock signal and the corresponding delayed data signal output from the multiplexer; and
a plurality of switches configured to couple the phase control circuit to the selected data receiver.

7. The skew compensation apparatus of claim 6 , wherein the selection signal is output from the phase control circuit.

8. The skew compensation apparatus of claim 6 , wherein the plurality of switches are controlled by the phase control circuit.

9. The skew compensation apparatus of claim 1 , further comprising a data storage configured to store the plurality of delayed data signals output from the plurality of data receivers in response to the clock signal.

10. The skew compensation apparatus of claim 9 , wherein the data storage comprises a plurality of flip-flop groups each configured to store one of the plurality of delayed data signals output from the plurality of data receivers in response to the clock signal.

11. The skew compensation apparatus of claim 1 , wherein data signals supplied to the plurality of data receivers are configured with data packets and a blank section between the data packets.

12. A skew compensation apparatus, comprising:
a plurality of data receivers each configured to delay a data signal supplied through a corresponding data line based on associated phase difference data and to output the delayed data signal;
a clock receiver configured to receive a clock signal supplied through a clock line; and
a phase controller configured to select one of the plurality of data receivers and to output, to the selected data receiver, a phase control signal configured to correct phase difference data of the selected data receiver based on a phase difference between a corresponding data signal output from the selected data receiver and the clock signal,
wherein data signals supplied to the plurality of data receivers are configured with data packets and a blank section between the data packets, and
wherein the phase controller is configured to output, to the selected data receiver, the phase control signal generated based on the phase difference between a null packet supplied during the blank section and the clock signal.

Assignees

• Samsung Display Co Ltd

Inventors

• Ahn Hee-Sun
• Lee Jae-Goo
• Shin Choong-Sun
• Won Young-Uk
• Song In-Bok

Classifications

• H04L7/0016 Primary

  correction of synchronization errors · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• H04L25/14 Primary

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title

• G06F2203/04111

  Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate · CPC title