Impedance adjustment method, delay capacitance adjustment method and associated apparatus for communication device

Patent metadata

Field	Value
Publication number	US-9484983-B2
Application number	US-201414327576-A
Country	US
Kind code	B2
Filing date	Jul 10, 2014
Priority date	Aug 15, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

An impedance adjustment method for a communication device, wherein the communication device has a plurality of impedance paths for selection, includes: selecting an initial impedance path; and utilizing a predetermined algorithm to examine a portion of the plurality of impedance paths by starting from the initial impedance path for selecting an optimized impedance path for the communication device. A delay capacitance adjustment method for a communication device, wherein the communication device has a plurality of delay capacitance paths for selection, includes: selecting an initial delay capacitance path; and utilizing a predetermined algorithm to examine a portion of the plurality of delay capacitance paths by starting from the initial delay capacitance path for selecting an optimized delay capacitance path of the communication device.

First claim

What is claimed is:

1. An impedance adjustment method for a communication device, wherein the communication device has a plurality of impedance paths for selection, the method comprising:
selecting an initial impedance path; and
utilizing an optimized impedance path generation unit within the communication device to use a predetermined algorithm to examine a portion of the plurality of impedance paths by starting from the initial impedance path for selecting an optimized impedance path for the communication device;
wherein the predetermined algorithm is a gradient descent method, and the step of utilizing the predetermined algorithm to examine the portion of the plurality of impedance paths by starting from the initial impedance path for selecting the optimized impedance path for the communication device comprises:
selecting a plurality of first impedance paths from the plurality of impedance paths to be a plurality of first candidate impedance paths according to a first specific selecting direction, a first specific step size, magnitude ordering of impedance of the plurality of impedance paths and the initial impedance path;
computing a plurality of first impedance path echo powers induced by the respective plurality of first candidate impedance paths;
comparing the plurality of first impedance path echo powers to generate a first comparison result; and
determining whether an optimized impedance path corresponding to the first specific step size is one of the plurality of first candidate impedance paths according to the first comparison result;
wherein the optimized impedance path of the communication device is determined according to the optimized impedance path corresponding to the first specific step size.

2. The impedance adjustment method of claim 1 , wherein the communication device is located in an Automotive Ethernet system.

3. The impedance adjustment method of claim 1 , wherein the step of utilizing the predetermined algorithm to examine the portion of the plurality of impedance paths by starting from the initial impedance path for selecting the optimized impedance path for the communication device further comprises:
when the first comparison result indicates that the optimized impedance path corresponding to the first specific step size does not exist within the plurality of first candidate impedance paths, selecting a plurality of second impedance paths from the plurality of impedance paths to update the plurality of first candidate impedance paths according to the plurality of first impedance paths, the first specific selecting direction, the first specific step size and the magnitude ordering of the impedance of the plurality of impedance paths.

4. The impedance adjustment method of claim 1 , wherein the step of determining whether the optimized impedance path corresponding to the first specific step size is one of the plurality of first candidate impedance paths according to the first comparison result comprises:
when the first comparison result indicates that a minimum impedance path echo power of the plurality of first impedance paths echo powers does not correspond to a first candidate impedance path having the maximum or minimum impedance compared to the rest of the plurality of first candidate impedance paths, determining a first candidate impedance path of the plurality of first candidate impedance paths corresponding to the minimum impedance path echo power to be the optimized impedance path corresponding to the first specific step size.

5. The impedance adjustment method of claim 1 , wherein the step of utilizing the predetermined algorithm to examine the portion of the plurality of impedance paths by starting from the initial impedance path for selecting the optimized impedance path for the communication device further comprises:
selecting a plurality of second impedance paths from the plurality of impedance paths to be a plurality of second candidate impedance paths according to a second specific selecting direction, a second specific step size, magnitude ordering of impedance of the plurality of impedance paths and the optimized impedance path corresponding to the first specific step size, wherein the second specific step size is smaller than the first specific step size, and the second specific selecting direction is the same as the first specific selecting direction or different from the first specific selecting direction;
computing a plurality of second impedance path echo powers induced by the respective plurality of second candidate impedance paths;
comparing the plurality of second impedance path echo powers to generate a second comparison result; and
determining whether an optimized impedance path corresponding to the second specific step size is one of the plurality of second candidate impedance paths according to the second comparison result;
wherein the optimized impedance path of the communication device is determined according to the optimized impedance path corresponding to the second specific step size.

6. The impedance adjustment method of claim 5 , wherein the step of utilizing the predetermined algorithm to examine the portion of the plurality of impedance paths by starting from the initial impedance path for selecting the optimized impedance path for the communication device further comprises:
when the second comparison result indicates that the optimized impedance path corresponding to the second specific step size does not exist within the plurality of second candidate impedance paths, selecting a plurality of third impedance paths from the plurality of impedance paths to update the plurality of second candidate impedance paths according to the plurality of second impedance paths, the second specific selecting direction, the second specific step size and the magnitude ordering of the impedance of the plurality of impedance paths.

7. The impedance adjustment method of claim 5 , wherein the step of determining whether the optimized impedance path corresponding to the first specific step size is one of the plurality of second candidate impedance paths according to the second comparison result comprises:
when the second comparison result indicates that a minimum impedance path echo power of the plurality of second impedance paths echo powers does not correspond to a second candidate impedance path having the maximum or minimum impedance compared to the rest of the plurality of second candidate impedance paths, determining a second candidate impedance path of the plurality of second candidate impedance paths corresponding to the minimum impedance path echo power to be the optimized impedance path corresponding to the second specific step size.

8. A delay capacitance adjustment method for a communication device, wherein the communication device has a plurality of delay capacitance paths for selection, the method comprising:
selecting an initial delay capacitance path; and
utilizing an optimized delay capacitance path generation unit within the communication device to use a predetermined algorithm to examine a portion of the plurality of delay capacitance paths by starting from the initial delay capacitance path for selecting an optimized delay capacitance path of the communication device;
wherein the predetermined algorithm is a gradient descent method, and the step of utilizing the predetermined algorithm to examine the portion of the plurality of delay capacitance paths by starting from the initial delay capacitance path for selecting the optimized delay capacitance path for the communication device comprises:
selecting a plurality of first delay capacitance paths from the plurality of delay capacitance paths to be a plurality of first candidate delay capacitance paths according to a first specific sele

Assignees

• Realtek Semiconductor Corp

Inventors

• Su Ching-Yao
• Huang Liang-Wei
• Wang Shih-Wei
• Ho Hsuan-Ting

Classifications

• H04L25/03885

  adaptive · CPC title

• H03H7/40

  Automatic matching of load impedance to source impedance · CPC title

• H04B3/20 Primary

  Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other · CPC title