Phase locked loop having fractional VCO modulation

Patent metadata

Field	Value
Publication number	US-9484936-B2
Application number	US-201514631305-A
Country	US
Kind code	B2
Filing date	Feb 25, 2015
Priority date	Feb 25, 2015
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.

First claim

What is claimed is:

1. An integrated circuit comprising:
a dual port modulator having a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing an integer portion of the high port modulation signal, and a third output for providing a low port signal, the fractional portion of the high port modulation signal generated using a signed single bit signal;
a sigma delta modulator to generate a low port modulation signal, the sigma delta modulator having an input for receiving a signal comprising a mix of a target frequency signal with the low port signal, and an output for providing the low port modulation signal;
a voltage controlled oscillator (VCO) coupled to the dual port modulator, the VCO having a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal.

2. The integrated circuit of claim 1 , wherein the fractional portion of the high port modulation signal is applied to the VCO at a higher clock rate than the integer portion of the high port modulation signal.

3. The integrated circuit of claim 1 , wherein the dual port modulator comprises a high port fractional modulator for producing the signed single bit signal used for generating the fractional portion of the high port modulation signal.

4. The integrated circuit of claim 3 , wherein the dual port modulator further comprises an integer fraction splitter circuit for receiving the high port modulation signal, for providing a first signal to the high port fractional modulator for generating the fractional portion of the high port modulation signal, and for providing a second signal for generating the integer portion of the high port modulation signal.

5. The integrated circuit of claim 3 , wherein the dual port modulator further comprises a binary to thermometric converter coupled to the high port fractional modulator for converting the signed single bit signal into a thermometric digital code for producing the high port modulation signal.

6. The integrated circuit of claim 3 , wherein the high port fractional modulator comprises a second order or higher sigma-delta modulator.

7. The integrated circuit of claim 6 , wherein the high port fractional modulator further comprises a quantizer coupled to the second order or higher sigma-delta modulator for producing the signed single bit signal.

8. The integrated circuit of claim 6 , further comprising a zero-mean dithering circuit coupled to the second order or higher sigma-delta modulator for mitigating idle tones in modulation.

9. The integrated circuit of claim 7 , wherein the signed single bit signal of the quantizer provides three signed states which are mapped to two thermometric varactors in the VCO.

10. A method of modulation comprising:
receiving a fractional portion of a high port modulation signal at a first input of a voltage controlled oscillator (VCO), the fractional portion of the high port modulation signal based on a signed single bit signal;
receiving an integer portion of the high port modulation signal at a second input of the VCO;
receiving a VCO tuning signal at a third input of the VCO;
generating a low port modulation signal with a sigma delta modulator, the sigma delta modulator receiving a signal comprising mixing a target frequency signal with a low port signal output at a third output of the dual port modulator, the VCO tuning signal based on the low port modulation signal; and
generating an RF signal at an output of the VCO.

11. The method of claim 10 , further comprising generating the fractional portion of a high port modulation signal at a first output of a dual port modulator and generating the integer portion of the high port modulation signal at a second output of the dual port modulator.

12. The method of claim 11 , further comprising generating, with an integer fraction splitter receiving the high port modulation signal, a first output signal and a second output signal based on the high port modulation signal.

13. The method of claim 12 , further comprising receiving the first output signal at a high port fractional modulator, the high port fractional modulator generating the signed single bit signal.

14. The method of claim 13 , further comprising receiving the signed single bit signal at a binary-to-thermometer code converter, and converting the signed single bit signal to a thermometric coded signal, the thermometric coded signal being characterized as the fractional portion of the high port modulation signal and provided to the first input of the VCO.

15. The method of claim 12 , further comprising generating the high port modulation signal by mixing a transmitter modulation signal with a calibration signal.

16. The method of claim 12 , further comprising generating the integer portion of the high port modulation signal by delaying the second output signal such that the integer portion of the high port modulation signal is aligned with the fractional portion of the high port modulation signal.

17. The method of claim 13 , wherein receiving the first output signal at a high port fractional modulator comprises dithering the first output signal.

18. An integrated circuit comprising:
a voltage controlled oscillator (VCO) for generating an RF signal, the VCO having a first input for receiving a fractional portion of a high port modulation signal, a second input for receiving an integer portion of the high port modulation signal, a third input for receiving a tuning signal;
a dual port modulator coupled to the VCO, the dual port modulator for receiving a transmitter modulation signal and for providing modulation signals to the VCO, the dual port modulator receiving the transmitter modulation signal at a first input, providing at a first output the fractional portion of the high port modulation signal based on a signed single bit signal, providing the integer portion of the high port modulation signal at a second output, and providing a low port signal at a third output; and
a sigma delta modulator to generate a low port modulation signal, the sigma delta modulator having an input for receiving a signal comprising a mix of a target frequency signal with the low port signal, and an output for providing the low port modulation signal, the tuning signal based on the low port modulation signal.

19. The method of claim 18 , wherein the RF signal is based on the tuning signal received at the VCO.

20. The integrated circuit of claim 18 , wherein the dual port modulator comprises a high port fractional modulator for producing the signed single bit signal used for generating the fractional portion of the high port modulation signal.

Assignees

• Freescale Semiconductor Inc

Inventors

• Waheed Khurram
• Traylor Kevin B

Classifications

• H03L7/0992 Primary

  comprising a counter or a frequency divider · CPC title

• H03B5/1265

  switched capacitors · CPC title

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title

• H03C3/0941

  applying frequency modulation at more than one point in the loop · CPC title

• H03C3/0975

  applying frequency modulation in the phase locked loop at components other than the divider, the voltage controlled oscillator or the reference clock · CPC title