Output driver with back-powering prevention

Patent metadata

Field	Value
Publication number	US-9484911-B2
Application number	US-201514631347-A
Country	US
Kind code	B2
Filing date	Feb 25, 2015
Priority date	Feb 25, 2015
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.

First claim

We claim:

1. An integrated circuit, comprising:
a pad configured to receive a voltage signal from a remote integrated circuit;
a power supply rail;
a first buffer transistor having a first terminal coupled to the pad and having a second terminal coupled to the power supply rail;
a pre-driver configured to drive a gate of the first buffer transistor through a first control path;
a first switch coupled between the first control path and the pad, the first switch being configured to switch on in response to a power down of the power supply rail; and
a control signal generator configured to respond to an assertion of the voltage signal while the power supply rail is powered down by coupling a body of the first buffer transistor to the pad.

2. The integrated circuit of claim 1 , further comprising:
a first transmission gate coupled between the pre-driver and the first control path, wherein the power supply rail couples to a gate of an NMOS transistor in the first transmission gate, and wherein the control signal generator is further configured to respond to the assertion of the voltage signal while the power supply rail is powered down by coupling a gate of a PMOS transistor in the first transmission gate to the pad.

3. The integrated circuit of claim 1 , wherein the first buffer transistor is a PMOS transistor, the first terminal is a drain, and the second terminal is a source, and the body is an n-well.

4. The integrated circuit of claim 1 , wherein the first switch comprises a switch PMOS transistor having a source coupled to the pad and a drain coupled to the first control path, and wherein the power supply rail couples to a gate of the switching PMOS transistor.

5. The integrated circuit of claim 4 , wherein the control signal generator is further configured to couple a body of the switch PMOS transistor to the pad in response to an assertion of the voltage signal while the power supply rail is powered down.

6. The integrated circuit of claim 2 , wherein the control signal generator comprises:
a first PMOS transistor having a source coupled to the pad and a drain coupled to the body of the first buffer transistor; and
an inverter having a power supply node coupled to the pad and having an input node coupled to the power supply rail and an output node coupled to the gate of the PMOS transistor in the first transmission gate.

7. The integrated circuit of claim 6 , wherein the control signal generator further comprises a second PMOS transistor having a source coupled to the power supply rail, a gate coupled to the output node of the inverter, and a drain coupled to the body of the first buffer transistor.

8. The integrated circuit of claim 1 , further comprising a second buffer transistor having a first terminal coupled to the pad and having a second terminal coupled to ground, wherein the pre-driver is further configured to drive a gate of the second buffer transistor through a second control path.

9. The integrated circuit of claim 8 , wherein the second buffer transistor comprises a buffer NMOS transistor having its drain coupled to the pad, a source coupled to ground, and a body coupled to ground.

10. The integrated circuit of claim 8 , further comprising a second switch coupled between the second control path and ground.

11. The integrated circuit of claim 10 , wherein the second switch comprises an NMOS switch transistor having a drain coupled to the second control path and a drain coupled to ground, and wherein the control signal generator is further configured to couple a gate of the NMOS switch transistor to the pad in response to the assertion of the voltage signal while the power supply rail is powered down.

12. The integrated circuit of claim 11 , wherein the control signal generator is further configured to couple the gate of the NMOS switch transistor to the power supply rail while the power supply rail is powered up.

13. The integrated circuit of claim 8 , further comprising a second transmission gate coupled between the pre-driver and the second control path, wherein the power supply rail is coupled to a gate of an NMOS transistor in the second transmission gate, and wherein the control signal generator is further configured to couple a gate of a PMOS transistor in the second transmission gate to the pad in response to the assertion of the voltage signal while the power supply rail is powered down.

14. The integrated circuit of claim 13 , wherein the control signal generator is further configured to couple the gate of the PMOS transistor in the second transmission gate to ground while the power supply rail is powered up.

15. A method, comprising
receiving an asserted voltage signal at an input/output (I/O) pin coupled to a first terminal of a first I/O buffer transistor while a power supply rail coupled to a second terminal of the first I/O buffer transistor is powered down;
in response to the receipt of the asserted voltage signal while the power supply rail is powered down, biasing a signal lead that couples to a gate of the first I/O buffer transistor with the asserted voltage signal; and
further in response to the receipt of the asserted voltage signal while the power supply rail is powered down, biasing a body of the first I/O buffer transistor with the asserted voltage signal.

16. The method of claim 15 , further comprising:
in response to a powering of the power supply rail, isolating both the signal lead and the body of the first I/O buffer transistor from the I/O pin; and
further in response to the powering of the power supply rail, coupling the body of the first I/O buffer transistor to the power supply rail.

17. The method of claim 15 , further comprising:
further in response to the receipt of the asserted voltage signal while the power supply rail is powered down, switching off a transmission gate coupled between the signal lead and a pre-driver.

18. A circuit, comprising:
a pad configured to receive a voltage signal from a remote integrated circuit;
a power supply rail;
a PMOS buffer transistor having a drain coupled to the pad and having a source terminal coupled to the power supply rail; and
means for coupling a body of the PMOS buffer transistor and a gate of the PMOS buffer transistor to the pad in response to a receipt of an asserted voltage signal at the pad while the power supply rail is powered down.

19. The circuit of claim 18 , further comprising:
a pre-driver configured to drive the gate of the PMOS buffer transistor through a first signal lead; and
a first transmission gate coupled between the first signal lead and the pre-driver; and
means for switching off the first transmission gate in response to the receipt of an asserted voltage signal at the pad while the power supply rail is powered down and for switching on the first transmission gate in response to the power supply rail being powered.

20. The circuit of claim 19 , further comprising:
an NMOS buffer transistor in series with the PMOS buffer transistor, wherein the pre-driver circuit is further configured to drive a gate of the NMOS buffer transistor through a second signal lead;
a second transmission gate coupled between the pre-driver and the second signal lead; and
means for grounding the second signal lead and switching off the second transmission gate in response to the receipt of an asserted voltage signal at the pad while the power supply rail is powered down.

Assignees

• Qualcomm Inc

Inventors

• Chen Wilson Jianbo
• Tan Chiew-Guan
• Jalilizeinali Reza

Classifications

• H03K17/26 Primary

  Modifications for temporary blocking after receipt of control pulses · CPC title

• H03K17/18

  Modifications for indicating state of switch · CPC title

• H03K19/00315 Primary

  in field-effect transistor circuits · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title