Self-adjusting duty cycle tuner

Patent metadata

Field	Value
Publication number	US-9484894-B2
Application number	US-201213544588-A
Country	US
Kind code	B2
Filing date	Jul 9, 2012
Priority date	Jul 9, 2012
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A duty cycle tuner measures high and low periods of a signal, calculates an actual duty cycle, generates duty control signals based on the actual duty cycle and a desired duty cycle, and adjusts the duty cycle responsive to the duty control signals. The high and low periods are measured using high-speed counters to provide a high count for the high period and a low count for the low period. The actual duty cycle value is then computed from the high and low counts, and compared to the desired duty cycle value to generate increment and decrement signals which may be positive or zero, to increase, decrease or maintain the actual duty cycle. In this manner, even if the high and low counts are subject to variations due to process, temperature or power supply voltage, their ratio is independent of such variations, so the tuner is immune to those effects.

First claim

What is claimed is:

1. A self-adjusting duty cycle tuner comprising:
a target signal input for receiving a target signal having a first frequency;
an input pulse generator which produces high-speed input pulses at a frequency greater than a frequency of the target signal;
a first counting circuit which receives the high-speed input pulses and the target signal, and derives a high count signal representing a high period of the target signal;
a second counting circuit which receives the high-speed input pulses and the target signal, and derives a low count signal representing a low period of the target signal;
a duty control logic circuit which receives the high count signal, the low count signal, a desired duty cycle value for the target signal, an increment threshold value and a decrement threshold value, then generates one or more duty control signals, wherein the one or more duty control signals include an increment signal and a decrement signal, the increment signal representing a first correction value for increasing the duty cycle of the target signal, and the decrement signal representing a second correction value for decreasing the duty cycle of the target signal, and wherein said duty control logic circuit includes a duty cycle arithmetic operation unit which implements add and divide operations using the high and low count signals and calculates an actual duty cycle value for the target signal, a comparator which activates a first output signal when the actual duty cycle value is smaller than the desired duty cycle value minus an increment threshold value and activates a second output signal when the actual duty cycle value is greater than the desired duty cycle value plus a decrement threshold value, a first subtractor which outputs a first amount by which the desired duty cycle exceeds the actual duty cycle, a second subtractor which outputs a second amount by which the actual duty cycle exceeds the desired duty cycle, a first multiplexer controlled by the first output signal of said comparator having input ports which receive a zero value and an output value of said first subtractor and having an output result which is the increment signal, and a second multiplexer controlled by the second output signal of said comparator having input ports which receive a zero value and an output value of said second subtractor and having an output result which is the decrement signal; and
a duty cycle controller which automatically adjusts the duty cycle of the target signal in response to the one or more duty control signals to provide an output signal having the desired duty cycle value.

2. The self-adjusting duty cycle tuner of claim 1 wherein the input pulse generator is a ring oscillator.

3. The self-adjusting duty cycle tuner of claim 1 wherein:
the first counting circuit includes
a NAND gate having two input ports which receive the high-speed input pulses and the target signal,
a first divider having an input port which receives high period pulses from an output port of said NAND gate, the high period pulses being high-speed input pulses occurring during a high state of the target signal,
a first counter having an input port which receives high count pulses from an output port of said first divider, and
a first register having an input port which receives a current high period measurement from an output port of said first counter, and holding an output result which provides the high count signal; and

the second counting circuit includes
a NOR gate having two input ports which receive the high-speed input pulses and the target signal,
a second divider having an input port which receives low period pulses from an output port of said NOR gate, the low period pulses being high-speed input pulses occurring during a low state of the target signal,
a second counter having an input port which receives low count pulses from an output port of said second divider, and
a second register having an input port which receives a current low period measurement from an output port of said second counter and holding an output result which provides the low count signal.

4. The self-adjusting duty cycle tuner of claim 1 wherein said duty cycle controller increases the duty cycle of the target signal as indicated by the increment signal, and decreases the duty cycle of the target signal as indicated by the decrement signal.

5. A clock control circuit comprising:
a clock source which provides an input clock signal;
a duty cycle controller which automatically adjusts a duty cycle of the input clock signal in response to an increment signal and a decrement signal to provide an output clock signal having a desired duty cycle;
a high-speed input pulse generator which produces high-speed input pulses at a frequency greater than a frequency of the input clock signal;
a first counting circuit which uses the high-speed input pulses to measure a high count for a high period of the input clock signal;
a second counting circuit which uses the high-speed input pulses to measure a low count for a low period of the input clock signal;
duty control logic which calculates an actual duty cycle value by performing add and divide operations using the high and low counts, compares the actual duty cycle value to a desired duty cycle value minus an increment threshold value and to the desired duty cycle value plus a decrement threshold value, and selectively sets the increment signal to indicate a first amount by which the duty cycle of the input clock signal should be increased when the actual duty cycle value is smaller than the desired duty cycle value minus the increment threshold value, sets the decrement signal to indicate a second amount by which the duty cycle of the input clock signal should be decreased when the actual duty cycle value is greater than the desired duty cycle value plus the decrement threshold value, and sets both the increment signal and the decrement signal to zero when the actual duty cycle value is equal to or greater than the desired duty cycle value minus the increment threshold value and the actual duty cycle value is equal to or smaller than the desired duty cycle value plus the decrement threshold value.

6. The clock control circuit of claim 5 wherein the ratio of the high and low counts is independent of variations in process, temperature and power supply voltage.

7. The clock control circuit of claim 5 wherein the increment and decrement signals are generated every time the high and low counts are updated.

8. An electronic system comprising:
a target circuit which receives at least one input signal and produces at least one output signal, said target circuit requiring a clock signal having a specific duty cycle;
a clock source which provides an input clock signal; and
a self-adjusting duty cycle tuner which automatically adjusts a duty cycle of the input clock signal to provide an output clock signal having the specific duty cycle to said target circuit, wherein said self-adjusting duty cycle tuner measures a high period of the input clock signal, measures a low period of the input clock signal, calculates an actual duty cycle of the input clock signal based on measurements of the high period and the low period, and generates one or more duty control signals based on the actual duty cycle and the specific duty cycle, wherein said self-adjusting duty cycle tuner uses high-speed counters to measure the high and low periods, calculates the actual duty cycle using counts values from the high-speed counters, compares the actual duty cycle to the specific duty cycle, sets an increment signal to indicate a first amount by which the duty cycle of the input clock signal should be increased when the actual duty cycle is smaller than the specific duty

Assignees

• Yasuda Takeo
• IBM

Inventors

• Yasuda Takeo

Classifications

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K2005/00247

  using counters · CPC title