Inducement of strain in a semiconductor layer

Patent metadata

Field	Value
Publication number	US-9484434-B2
Application number	US-201314103521-A
Country	US
Kind code	B2
Filing date	Dec 11, 2013
Priority date	Dec 8, 2006
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.

First claim

What is claimed is:

1. A method for forming a structure, the method comprising:
forming a first crystalline semiconductor layer over a substrate, the first crystalline semiconductor layer being strained and having a first lattice constant;
forming a second crystalline semiconductor layer on a top surface of the first crystalline semiconductor layer, the second crystalline semiconductor layer being relaxed and having a lattice constant different from the first lattice constant;
forming a transistor including a gate electrode disposed above the second crystalline semiconductor layer, a sidewall spacer adjacent the gate electrode, and a channel region disposed below the gate electrode and at least partially in the second crystalline semiconductor layer; and
creating a free surface above the channel region in at least one of the gate electrode or the sidewall spacer, wherein the free surface induces strain in at least a portion of the channel region disposed in the second crystalline semiconductor layer.

2. The method of claim 1 , wherein creating the free surface above the channel region induces relaxation of strain in the first crystalline semiconductor layer disposed below the channel region.

3. The method of claim 1 , wherein creating the free surface above the channel region comprises removing the sidewall spacer.

4. The method of claim 1 , wherein creating the free surface above the channel region comprises amorphizing and annealing at least a portion of the gate electrode.

5. The method of claim 1 , wherein the gate electrode comprises an amorphous material and creating the free surface above the channel region comprises thermally annealing the gate electrode.

6. The method of claim 1 , further comprising forming a strain-inducing overlayer above the first crystalline semiconductor layer.

7. A method for forming a structure, the method comprising:
forming a first crystalline semiconductor material over a substrate, the first crystalline semiconductor material being strained and having a first lattice constant;
forming a second crystalline semiconductor material over the first crystalline semiconductor material, the second crystalline semiconductor material having a second lattice constant different from the first lattice constant, the second crystalline semiconductor material having a first strain; and
relaxing strain in a first portion of the first crystalline semiconductor material and inducing strain in a first portion of the second crystalline semiconductor material to a second strain, the second strain being greater than the first strain, the first portion of the second crystalline semiconductor material overlying the first portion of the first crystalline semiconductor material.

8. The method of claim 7 , wherein the step of relaxing strain and inducing strain comprises:
performing an amorphization implant in a second portion of the first crystalline semiconductor material and a second portion of the second crystalline semiconductor material to form the second portion of the first crystalline semiconductor material into a first amorphized material and to form the second portion of the second crystalline semiconductor material into a second amorphized material; and
annealing the first amorphized material and the second amorphized material.

9. The method of claim 7 , wherein the step of relaxing strain and inducing strain comprises defining a free surface in the first crystalline semiconductor material and the second crystalline semiconductor material.

10. The method of claim 7 , wherein the step of relaxing strain and inducing strain comprises etching a recess in the first crystalline semiconductor material and the second crystalline semiconductor material.

11. The method of claim 7 , further comprising forming a gate structure over the second crystalline semiconductor material, the gate structure comprising a third crystalline material, wherein the step of relaxing strain and inducing strain comprises:
performing an amorphization implant in the third crystalline material to form the third crystalline material into an amorphized material; and
annealing the amorphized material.

12. The method of claim 7 , wherein the first crystalline semiconductor material comprises an alloy of silicon and germanium, and wherein the second crystalline semiconductor material consists essentially of silicon.

13. The method of claim 7 further comprising forming a relaxed third material adjacent the first portion of the second crystalline semiconductor material and the first portion of the first crystalline semiconductor material.

14. The method of claim 7 , wherein the substrate comprises silicon.

15. A method for forming a structure, the method comprising:
forming a first crystalline semiconductor material over a substrate, the first crystalline semiconductor material being strained and having a first lattice constant;
forming a second crystalline semiconductor material over the first crystalline semiconductor material, the second crystalline semiconductor material having a second lattice constant different from the first lattice constant;
forming a gate structure over the second crystalline semiconductor material, the gate structure defining a region underlying the gate structure;
amorphizing a portion of the gate structure, a portion of the first crystalline semiconductor material, and a portion of the second crystalline semiconductor material, the portion of the first crystalline semiconductor material and the portion of the second crystalline semiconductor material being at least part of a source/drain region proximate the region underlying the gate structure; and
annealing the portion of first crystalline semiconductor material and the portion of the second crystalline semiconductor material.

16. The method of claim 15 , wherein the forming the gate structure comprises forming a sidewall spacer laterally adjacent to a gate electrode, wherein after the amorphizing and before the annealing, the sidewall spacer is removed.

17. The method of claim 15 , wherein the first crystalline semiconductor material comprises an alloy of silicon and germanium, and wherein the second crystalline semiconductor material consists essentially of silicon.

18. The method of claim 15 , wherein the substrate comprises silicon.

19. A method for forming a structure, the method comprising:
forming a first crystalline semiconductor material over a substrate, the first crystalline semiconductor material being strained and having a first lattice constant;
forming a second crystalline semiconductor material over the first crystalline semiconductor material, the second crystalline semiconductor material having a second lattice constant different from the first lattice constant;
forming a gate structure over the second crystalline semiconductor material, the gate structure comprising a third crystalline material;
performing an amorphization implant in a first portion of the first crystalline semiconductor material, a first portion of the second crystalline semiconductor material, and the third crystalline material to form the first portion of the first crystalline semiconductor material into a first amorphized material, the first portion of the second crystalline semiconductor material into a second amorphized material, and the third crystalline material into a third amorphized material; and
annealing the first amorphized material, the second amorphized material, and the third amorphized material.

20. The method of claim 19 , wherein the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fiorenza James
• Carroll Mark
• Lochtefeld Anthony J

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10P30/21 Primary

  of electrically active species · CPC title