Methods of forming buried junction devices in silicon carbide using ion implant channeling and silicon carbide devices including buried junctions

Patent metadata

Field	Value
Publication number	US-9484413-B2
Application number	US-201414297074-A
Country	US
Kind code	B2
Filing date	Jun 5, 2014
Priority date	Jul 26, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron.

First claim

That which is claimed is:

1. A semiconductor device, comprising:
a silicon carbide substrate having a first conductivity type;
a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate; and
a buried junction structure in the silicon carbide drift layer, wherein the buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about two microns;
wherein the buried junction structure comprises floating regions of the second conductivity type;
wherein the buried junction structure has a thickness of from about 1.5 microns to about 3 microns.

2. The semiconductor device of claim 1 , wherein the silicon carbide drift layer comprises an upper drift layer and a lower drift layer separated by the buried junction structure, wherein the lower drift layer is between the substrate and the upper drift layer, and wherein the upper drift layer has a thickness that is greater than about one micron.

3. The semiconductor device of claim 2 , wherein the buried junction structure has a junction depth, and wherein the semiconductor device has a radius of curvature that is equal to a thickness of the lower drift layer less the junction depth of the buried region, wherein the radius of curvature is less than a lateral width of the lower drift layer.

4. The semiconductor device of claim 1 , wherein the junction depth of the buried junction structure is greater than about 2 microns.

5. The semiconductor device of claim 1 , wherein the junction depth of the buried junction structure is greater than about 4 microns.

6. The semiconductor device of claim 1 , wherein the buried junction structure comprises a plurality of buried regions arranged in a grid.

7. The semiconductor device of claim 6 , wherein the plurality of buried regions are electrically isolated from one another.

8. The semiconductor device of claim 1 , wherein the buried junction structure comprises a first buried junction structure having a first junction depth, and wherein the semiconductor device further comprises a second buried junction structure having a second junction depth that is different from the first junction depth.

9. The semiconductor device of claim 8 , wherein the first and second buried junction structures are electrically isolated from one another.

10. The semiconductor device of claim 1 , further comprising a junction termination structure adjacent an active region of the device, wherein the junction termination structure has a junction depth that is about equal to the junction depth of the buried junction structure.

11. The semiconductor device of claim 1 , wherein the buried junction structure comprises a first buried junction structure having a first junction depth, and wherein the semiconductor device further comprises a second buried junction structure having a second junction depth that is greater than the first junction depth.

12. A method of forming an electronic device, comprising:
providing a silicon carbide drift layer having a first conductivity type and a first doping concentration and having a crystallographic axis; and
implanting dopant ions to a depth of greater than about one micron in the silicon carbide drift layer to form a buried junction structure in the silicon carbide drift layer, wherein the buried junction structure has a second conductivity type that is opposite the first conductivity type and has a second doping concentration that is greater than the first doping concentration, wherein implanting the dopant ions comprises implanting the dopant ions at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°.

13. The method of claim 12 , wherein the implant angle is greater than 0.1°.

14. The method of claim 12 , wherein the implant angle is between 0.1° and 1°.

15. The method of claim 12 , wherein the implant angle is between 0.1° and 5°.

16. The method of claim 15 , wherein the silicon carbide drift layer has a thickness of from about 15 microns to about 200 microns.

17. The method of claim 12 , wherein the buried junction structure has a junction depth of from about 2.5 microns to about 4.5 microns into the drift layer.

18. The method of claim 12 , wherein the buried junction structure has a doping concentration of from about 1E17 cm −3 to about 1E20 cm −3 .

19. The method of claim 12 , wherein the buried junction structure comprises a first buried junction structure having a first junction depth, the method further comprising forming a second buried junction structure in the silicon carbide drift layer, the second buried junction structure having a second junction depth that is different from the first junction depth.

Assignees

• Cree Inc

Inventors

• Van Brunt Edward Robert
• Suvorov Alexander V
• Pala Vipindas
• Cheng Lin

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/2042 Primary

  into crystalline silicon carbide · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title