Systems and methods for fabricating cross-pillar superjunction structures for semiconductor power conversion devices
US-2024038836-A1 · Feb 1, 2024 · US
US9484400B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9484400-B2 |
| Application number | US-201514878565-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 8, 2015 |
| Priority date | Oct 31, 2012 |
| Publication date | Nov 1, 2016 |
| Grant date | Nov 1, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A super junction semiconductor device is formed by forming at least a portion of a drift layer on a doped layer of a first conductivity type, implanting first dopants of a first conductivity type and second dopants of a second conductivity type into the drift layer using one or more implant masks with openings to form stripe-shaped first implant regions of the first conductivity type and stripe-shaped second implant regions of the second conductivity type in alternating order, and performing a heat treatment for controlling a diffusion of dopants from the implant regions to form stripe-shaped first regions of the first conductivity type and stripe-shaped second regions of the second conductivity type.
Opening claim text (preview).
What is claimed is: 1. A method of forming a super junction semiconductor device, the method comprising: forming at least a portion of a drift layer on a doped layer of a first conductivity type; implanting first dopants of a first conductivity type and second dopants of a second conductivity type into the drift layer using one or more implant masks with openings to form stripe-shaped first implant regions of the first conductivity type, stripe-shaped second implant regions of the second conductivity type in alternating order and a circumferential implant zone of the first conductivity type that encloses the stripe-shaped first and second regions, wherein the stripe-shaped second implant regions are separated from the stripe-shaped first implant regions and from the circumferential implant zone at uniform distances; performing a heat treatment for controlling a diffusion of dopants from the implant regions to form stripe-shaped first regions of the first conductivity type and stripe-shaped second regions of the second conductivity type. 2. The method of claim 1 , wherein the diffusion is controlled such that neighboring ones of the stripe-shaped first and second regions directly adjoin each other. 3. The method of claim 1 , wherein the stripe-shaped first implant regions are formed longer than the stripe-shaped second implant regions. 4. The method of claim 1 , wherein the circumferential implant zone includes one stripe or two or more parallel stripes. 5. The method of claim 1 , wherein the stripe-shaped first implant regions are formed connected with the implant region of the circumferential implant zone. 6. The method of claim 1 , wherein the stripe-shaped second implant regions are formed separated from the implant region of the circumferential implant zone. 7. The method of claim 1 , wherein the implant region of the circumferential implant zone is formed wider than the stripe-shaped first and second implant regions resulting in a higher effective doping concentration in the circumferential implant zone. 8. The method of claim 1 , wherein the circumferential implant zone of the first conductivity type surrounds the stripe-shaped first and second regions in an outer portion of an edge area devoid of the stripe-shaped second regions, the outer portion adjoining an edge of a semiconductor body that comprises the drift layer, wherein the circumferential implant zone has an inner edge comprising a corner portion corresponding to a corner of the semiconductor body, the corner portion having a concave shape, and wherein minimum distances between each of the stripe-shaped second regions and the circumferential implant zone are equal. 9. The method of claim 8 , wherein the corner portion comprises a first portion forming a segment of a circle and a second, straight portion slanted to orthogonal portions of the circumferential implant zone, the first portion joining to a portion of the inner edge running orthogonal to the stripe-shaped first and second regions and the second portion joining to a portion of the inner edge running parallel to the stripe-shaped first and second regions. 10. The method of claim 8 , wherein the stripe-shaped first and second regions each have lower dopant levels in the edge area than in the cell area by at least 10%. 11. The method of claim 8 , wherein the dopant levels of the stripe-shaped first and second regions are reduced in steps in a transition area between the edge area and a cell area that includes doped zones adjoining to a first surface, and wherein the dopant levels are reduced from first dopant levels in the cell area to second dopant levels in the edge area, the second dopant levels being at least 10% lower than the first dopant levels. 12. The method of claim 11 , wherein the transition area has a corner portion connecting two orthogonal portions of the transition area at a slope angle of 45 degrees, the corner portion having a width which is the width of the orthogonal portions divided by √{square root over (2)}, and wherein dopant levels of the stripe-shaped first and second regions are reduced at the same rate in orthogonal direction in the orthogonal and the corner portions. 13. The method of claim 1 , wherein the diffusion is controlled such that neighboring ones of the stripe-shaped first and second regions remain separated from each other.
Thermal treatments, e.g. annealing or sintering · CPC title
within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title
of electrically inactive species · CPC title
into Group IV semiconductors · CPC title
using masks · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.