Semiconductor device including switch electrically connected to signal line

Patent metadata

Field	Value
Publication number	US-9484365-B2
Application number	US-201414448180-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Jan 15, 2010
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

To suppress variation of a signal in a semiconductor device. By suppressing the variation, formation of a stripe pattern in displaying an image on a semiconductor device can be suppressed, for example. A distance between two adjacent signal lines which go into a floating state in different periods (G1) is longer than a distance between two adjacent signal lines which go into a floating state in the same period (G0, G2). Consequently, variation in potential of a signal line due to capacitive coupling can be suppressed. For example, in the case where the signal line is a source signal line in an active matrix display device, formation of a stripe pattern in a displayed image can be suppressed.

First claim

What is claimed is:

1. A semiconductor device comprising:
first to n-th transistors (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period;
(n+1)-th to m-th transistors (m is a natural number of n+2 or more) configured to be turned off in the first period and turned on in the second period;
first to n-th signal lines; and
(n+1)-th to m-th signal lines,
wherein the first to m-th signal lines are parallel,
wherein a distance between the n-th signal line and the (n+1)-th signal line is longer than a distance between the (n−1)-th signal line and the n-th signal line and is longer than a distance between the (n+1)-th signal line and the (n+2)-th signal line, and
wherein one of a source terminal and a drain terminal of the n-th transistor is closer to the (n+1)-th transistor than the other of the source terminal and the drain terminal of the n-th transistor.

2. The semiconductor device according to claim 1 ,
wherein a signal is supplied to any one of the first to n-th signal lines and to any one of the (n+1)-th to m-th signal lines through a same wiring.

3. The semiconductor device according to claim 1 ,
wherein m=2n.

4. The semiconductor device according to claim 1 ,
wherein the first to m-th transistors are spaced at regular intervals, and channel length directions of the first to m-th transistors are perpendicular or approximately perpendicular to the first to m-th signal lines,
wherein one of a source terminal and a drain terminal of the (n+1)-th transistor is closer to the n-th transistor than the other of the source terminal and the drain terminal of the (n+1)-th transistor,
wherein the other of the source terminal and the drain terminal of the n-th transistor is electrically connected to the n-th signal line, and
wherein the other of the source terminal and the drain terminal of the (n+1)-th transistor is electrically connected to the (n+1)-th signal line.

5. The semiconductor device according to claim 1 ,
wherein channel formation regions of the first to m-th transistors comprise an oxide semiconductor.

6. The semiconductor device according to claim 1 ,
wherein a shift register circuit which controls switching of the first to m-th transistors is included, and
wherein the shift register circuit includes a transistor whose channel formation region comprises an oxide semiconductor.

7. The semiconductor device according to claim 1 ,
wherein an electronic device comprises the semiconductor device.

8. A semiconductor device comprising:
a first set of first to n-th switches (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period and a third period;
a second set of (n+1)-th to 2n-th switches configured to be turned on in the second period and turned off in the first period and the third period;
a third set of (2n+1)-th to 3n-th switches configured to be turned on in the third period and turned off in the first period and the second period;
a fourth set of first to n-th signal lines;
a fifth set of (n+1)-th to 2n-th signal lines; and
a sixth set of (2n+1)-th to 3n-th signal lines,
wherein a signal is supplied to any one of the first to n-th signal lines, to any one of the (n+1)-th to 2n-th signal lines, and to any one of the (2n+1)-th to 3n-th signal lines through a same wiring,
wherein the first to 3n-th signal lines are parallel,
wherein a distance between the n-th signal line and the (n+1)-th signal line is longer than a distance between the (n−1)-th signal line and the n-th signal line and is longer than a distance between the (n+1)-th signal line and the (n+2)-th signal line, and
wherein a distance between the 2n-th signal line and the (2n+1)-th signal line is longer than a distance between the (2n−1)-th signal line and the 2n-th signal line and is longer than a distance between the (2n+1)-th signal line and the (2n+2)-th signal line.

9. The semiconductor device according to claim 8 ,
wherein the first to 3n-th switches are first to 3n-th transistors.

10. The semiconductor device according to claim 9 ,
wherein the first to 3n-th transistors are spaced at regular intervals, and channel length directions of the first to 3n-th transistors are perpendicular or approximately perpendicular to the first to 3n-th signal lines,
wherein one of a source terminal and a drain terminal of the n-th transistor is closer to the (n+1)-th transistor than the other of the source terminal and the drain terminal of the n-th transistor,
wherein one of a source terminal and a drain terminal of the (n+1)-th transistor is closer to the n-th transistor than the other of the source terminal and the drain terminal of the (n+1)-th transistor,
wherein the other of the source terminal and the drain terminal of the n-th transistor is electrically connected to the n-th signal line, and
wherein the other of the source terminal and the drain terminal of the (n+1)-th transistor is electrically connected to the (n+1)-th signal line.

11. The semiconductor device according to claim 10 ,
wherein one of a source terminal and a drain terminal of the 2n-th transistor is closer to the (2n+1)-th transistor than the other of the source terminal and the drain terminal of the 2n-th transistor,
wherein one of a source terminal and a drain terminal of the (2n+1)-th transistor is closer to the 2n-th transistor than the other of the source terminal and the drain terminal of the (2n+1)-th transistor,
wherein the other of the source terminal and the drain terminal of the 2n-th transistor is electrically connected to the 2n-th signal line, and
wherein the other of the source terminal and the drain terminal of the (2n+1)-th transistor is electrically connected to the (2n+1)-th signal line.

12. The semiconductor device according to claim 9 ,
wherein channel formation regions of the first to m-th transistors comprise an oxide semiconductor.

13. The semiconductor device according to claim 9 ,
wherein a shift register circuit which controls switching of the first to 3n-th transistors is included, and
wherein the shift register circuit includes a transistor whose channel formation region comprises an oxide semiconductor.

14. The semiconductor device according to claim 8 ,
wherein an electronic device comprises the semiconductor device.

Assignees

• Semiconductor Energy Lab

Inventors

• Shishido Hideaki

Classifications

• G02F1/133305

  Flexible substrates, e.g. plastics, organic film · CPC title

• G02F1/13454

  Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence) · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title