Memory device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9484353-B1
Application number	US-201514803218-A
Country	US
Kind code	B1
Filing date	Jul 20, 2015
Priority date	Jul 20, 2015
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A memory device includes a first insulating layer, a second insulating layer, an isolation layer, a floating gate electrode, a control gate electrode, a channel layer and a tunneling oxide layer. The second insulating layer is disposed adjacent to and substantially parallel with the first insulating layer to form an interlayer space there between. The isolation layer is disposed in the interlayer space to form a non-straight angle with the first insulating layer, and divides the interlayer space into a first recess and a second recess. The floating gate electrode is disposed in the first recess. The control gate electrode is disposed in the second recess. The channel layer is disposed on an opening surface of the first recess and forms a non-straight angle with the first insulating layer. The tunneling oxide layer is disposed between the channel layer and the floating gate electrode.

First claim

What is claimed is:

1. A method for fabricating a memory device, comprising:
providing a multilayers stack having a plurality of insulating layers and a plurality of sacrificing layers alternatively stacked with each other;
forming at least one first through opening passing through the multilayers stack to partially expose the insulating layers and the sacrificing layers;
performing a pull-back etching process to remove portions of the sacrificing layers through the first through opening, whereby a plurality of first recesses are defined by the remaining sacrificing layers and the insulating layers;
partially oxidizing the remaining sacrificing layers to form an insulation layer in each of the first recess;
forming a plurality of floating gate electrodes to respectively fill the first recess;
forming a tunneling oxide layer to cover portions of the insulating layer and the floating gate electrodes exposed from the first through opening;
forming a channel layer on the tunneling oxide layer;
forming at least one second through opening passing through the multilayers stacks to partially expose the insulating layers and the remaining sacrificing layers;
removing the remaining sacrificing layers to expose portions of the isolation layers, whereby a plurality of second recesses are defined by the insulating layers and the isolation layers; and
forming a plurality of control gates to respectively fill in the second recesses.

2. The method according to claim 1 , wherein the process of oxidizing the remaining sacrificing layers comprises an in-situ steam generation (ISSG) oxidation process used to transform silicon nitride of the remaining sacrificing layer into silicon oxide to form the isolation layers.

3. The method according to claim 1 , further comprising steps of performing a nitridation process to form a first lining layer covering on portions of the insulating layers and the isolation layers exposed from the first recesses, prior to the forming of the floating gate electrodes.

4. The method according to claim 1 , wherein the process of forming the floating gate electrodes comprises:
forming a conductive layer to fill the first through opening and the first recesses; and
performing a pull-back etching process to remove portions of the conductive layer disposed in the first through opening.

5. The method according to claim 1 , further comprising steps of performing a nitridation process to form a second lining layer covering on portions of the insulating layers and the isolation layers exposed from the second recesses, prior to the forming of the control gate electrodes.

6. The method according to claim 1 , wherein the process of forming the control gate electrodes comprises:
forming a gate dielectric layer to blanket over portions of the insulating layer and the isolation layers exposed from the second through opening and the second recesses;
forming a metal layer on the gate dielectric layer, so as to fill the second recesses; and performing a metal pullback etching process to remove portions of the metal layer and the gate dielectric layer disposed in the second through opening.

7. The method according to claim 1 , wherein the first through opening is a through hole, the second through opening is a trench, and tunneling oxide layer and the channel layer are surrounded by the floating gate electrodes and the isolation layers.

8. The method according to claim 7 , further comprising steps of filling a dielectric material into the first through opening and forming at least one air gap in the filled first through opening, prior to the forming of the second through opening.

9. The method according to claim 1 , wherein the first through opening is a trench, and the second through opening is a through hole.

10. The method according to claim 9 , further comprising steps of thoroughly filling the first through opening with a spin-on-dielectric (SOD) material, prior to the forming of the second through opening.

11. The method according to claim 1 , wherein the multilayers stack is formed on a common source layer and the channel is electrically contact with the common source layer.

12. The method according to claim 11 , further comprising steps of forming a protection layer on the multilayers stack.

13. The method according to claim 1 , wherein the multilayers stack is formed on a bottom insulating layer and the channel has a U-shaped cross-sectional profile extending into the bottom insulating layer.

14. The method according to claim 1 , prior to the forming of the second through opening, further comprising:
forming a bond pad layer on the multilayers stack and electrically connected to the channel layer; and
forming a protection layer to cover the multilayers stack and the bond pad layer.

Assignees

• Macronix Int Co Ltd

Inventors

• Lai Erh-Kun
• Chen Wei-Chen
• Lee Dai-Ying

Classifications

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/689 Primary

  Vertical floating-gate IGFETs · CPC title

• H01L29/16

  Electricity · mapped topic

• H01L29/7883

  Electricity · mapped topic

• H01L21/0223

  Electricity · mapped topic