Insulated gate bipolar transistor with a free wheeling diode

Patent metadata

Field	Value
Publication number	US-9484343-B2
Application number	US-201514641984-A
Country	US
Kind code	B2
Filing date	Mar 9, 2015
Priority date	Jun 25, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n + impurity layer on the whole back surface of n − semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n + cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p + impurity layer in the interior of the n + impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p + the n + impurity layers activated.

First claim

What is claimed is:

1. A reverse-conducting semiconductor device comprising:
an insulated-gate bipolar transistor portion comprising:
a drift layer of a first conductivity type,
a base layer of a second conductivity type selectively formed on the front surface of the drift layer ( 1 ),
an emitter region of the first conductivity type selectively formed on the surface of the base layer,
a trench formed from the surface of the base layer into the drift layer,
a gate oxide formed on the inner sidewall of the trench,
a gate electrode formed to face the base layer and the emitter region sandwiched between the gate oxide,
a field stop layer of the first conductivity type formed on the rear side surface of the drift layer,
a collector layer of the second conductivity type formed on the rear side surface of the field stop layer,
a free-wheeling diode portion adjacent to the insulated-gate bipolar transistor portion, wherein the drift layer and the field stop layer extends from the insulated-gate bipolar transistor portion,
an anode layer of a second conductivity type selectively formed on the front surface of the drift layer, and
a cathode layer of the first conductivity type formed on the rear side surface of the field stop layer,
wherein R p 1, ΔR p 1, R p 2, and ΔR p 2 are defined as the position of the peak concentration of the cathode layer, the standard deviation of the concentration of the cathode layer, the position of the peak concentration of the collector layer, and the standard deviation of the concentration of the collector layer, respectively, and
wherein the following equation 1 is satisfied as:
R p 2+3Δ R p 2≧ R p 1+3Δ R p 1  (1)

2. The reverse conducting semiconductor device according to claim 1 ,
wherein N 1 , N 2 , xj 1 , and xj 2 are defined as dose of the collector layer, dose of the cathode layer, diffusion depth of the cathode layer, and diffusion depth of the collector layer, respectively,
wherein the following equation 2 is satisfied as:
N 2> N 1·( xj 2/ xj 1)  (2).

3. The reverse conducting semiconductor device according to claim 2 , wherein the dose of the collector layer is equal to or greater than 1.0×10 15 cm −2 .

4. The reverse conducting semiconductor device according to claim 1 , wherein a dose of the collector layer is equal to or greater than 1.0×10 15 cm −2 .

Assignees

• Fuji Electric Co Ltd

Inventors

• Noguchi Seiji
• Kuribayashi Hidenao

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P32/1406 Primary

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title