Electronic system with a composite substrate

Patent metadata

Field	Value
Publication number	US-9484290-B2
Application number	US-201313969604-A
Country	US
Kind code	B2
Filing date	Aug 18, 2013
Priority date	Feb 12, 2010
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A composite substrate made of a conductive pattern structure mounted on a lead frame is used for an electronic system package. High heat generated electronic components are adapted to mount on the lead frame and relatively low heat generated electronic components are adapted to mount on the conductive pattern structure. Metal lines are used for electrical coupling between the circuitry of the IC chip and the conductive pattern structure. An electronic system with the composite substrate gains both advantages—good circuitry arrangement capability from the conductive pattern structure and good heat distribution from the lead frame.

First claim

What is claimed is:

1. An electronic system with a composite substrate, comprising:
a lead frame having a chip mounting area and a plurality of metal leads arranged along a periphery of said chip mounting area, wherein each of the plurality of metal leads is spaced from said chip mounting area by a gap;
a conductive pattern structure disposed over said lead frame and having circuitry, said conductive pattern structure bridging the gap between each said metal lead and said chip mounting area; and
a chip, mounted on said chip mounting area of said lead frame and electrically coupling to the circuitry of said conductive pattern structure, wherein a bottom surface of said conductive pattern structure comprises a plurality of contacts and a bottom surface of each of the plurality of metal leads that is located below a bottom surface of said chip extends upright to a portion of the top surface of the metal lead that is in contact with and electrically connected to a corresponding contact of said conductive pattern structure.

2. The electronic system according to claim 1 , wherein the chip mounting area is substantially flat.

3. The electronic system according to claim 2 , wherein the top surface of the metal leads of the lead frame and the top surface of the chip are substantially at the same horizontal level to form a flat surface for disposing the plurality of the conductive layers over the flat surface.

4. The electronic system according to claim 1 , wherein the bottom surface of said conductive pattern structure encapsulates the chip.

5. The electronic system according to claim 1 , wherein said conductive pattern structure comprises a plurality of conductive pattern layers disposed over the said lead frame and the chip to electrically connect each said metal lead and the chip.

6. The electronic system according to claim 5 , wherein said plurality of conductive pattern layers are formed over the said lead frame and the chip by lithography process.

7. The electronic system according to claim 5 , wherein said chip comprises a plurality of pins, wherein said pins are electrically coupling to the circuitry of the conductive pattern structure through the plurality of conductive pattern layers.

8. The electronic system according to claim 1 , further comprising at least one electronic component disposed on the top surface of said conductive pattern structure, wherein said at least one electronic component is electrically coupling to the circuitry of said conductive pattern structure.

9. The electronic system according to claim 1 , further comprising: a molding compound to encapsulate said lead frame to form a first flat surface before disposing the conductive pattern structure over the first flat surface.

10. The electronic system according to claim 1 , further comprising a molding compound to encapsulate the lead frame, the chip and the conductive pattern structure, wherein at least one portion of said bottom surface of each metal lead that is located below said bottom surface of the chip is exposed outside the molding compound for connecting with an external circuit.

11. The electronic system according to claim 1 , wherein the chip is a semiconductor die with a plurality of I/O contacts.

12. The electronic system according to claim 1 , wherein the top surface of said conductive pattern structure further comprises additional contacts that are electrically coupling to the circuitry of the conductive pattern structure and said chip.

13. The electronic system according to claim 1 , wherein said conductive pattern structure is a circuit board.

14. An electronic system with a composite substrate, comprising:
a lead frame having a metal body and a plurality of metal leads arranged along a periphery of said metal body, wherein each of the plurality of metal leads is spaced from said metal body by a gap;
a conductive pattern structure disposed over said lead frame and having circuitry, said conductive pattern structure bridging the gap between each said metal lead and said metal body; and
an electronic component, disposed on said metal body of said lead frame and electrically coupling to the circuitry of said conductive pattern structure, wherein a bottom surface of said conductive pattern structure comprises a plurality of contacts and a bottom surface of each of the plurality of metal leads that is located below a bottom surface of said electronic component extends upright to a portion of the top surface of the metal lead that is in contact with and electrically connected to a corresponding contact of said conductive pattern structure.

15. The electronic system according to claim 14 , wherein said conductive pattern structure is a circuit board.

16. The electronic system according to claim 14 , further comprising a molding compound to encapsulate the lead frame, the electronic component and said conductive pattern structure, wherein at least one portion of said bottom surface of each metal lead that is located below said bottom surface of the electronic component is exposed outside the molding compound for connecting with an external circuit.

Assignees

• Cyntec Co Ltd
• Cyntec Co Ltd

Inventors

• Lee Han-Hsiang
• Li Jeng-Jen
• Shih Kun-Hong

Classifications

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W70/468

  Circuit boards · CPC title

• H10W70/421

  Shapes or dispositions · CPC title

• H05K7/14322

  wherein the control and power circuits of a power converter are arranged within the same casing · CPC title