Methods for fabricating strained gate-all-around semiconductor devices by fin oxidation using an undercut etch-stop layer

Patent metadata

Field	Value
Publication number	US-9484272-B2
Application number	US-201414266643-A
Country	US
Kind code	B2
Filing date	Apr 30, 2014
Priority date	Sep 27, 2012
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a three-dimensional semiconductor structure on an epitaxial seed layer disposed above a semiconductor substrate, the epitaxial seed layer comprising a semiconductor material different from the three-dimensional semiconductor structure;
etching the three-dimensional semiconductor structure to provide a three-dimensional channel region and to expose portions of the epitaxial seed layer on either side of the three-dimensional channel region;
forming source and drain regions on either side of the three-dimensional channel region and on the epitaxial seed layer;
insulating the three-dimensional channel region and the source and drain regions from the semiconductor substrate by forming an insulating structure comprising one or more isolation pedestals, the insulating structure continuous with the semiconductor substrate; and, subsequently,
removing a portion of the epitaxial seed layer;
forming a gate electrode stack at least partially surrounding the three-dimensional channel region; and
forming a pair of conducting contacts, one contact at least partially surrounding the source region, and another contact at least partially surrounding the drain region, wherein removing the portion of the epitaxial seed layer comprises removing a portion between the source and drain regions and the semiconductor substrate, and wherein the one contact surrounds the source region and the other contact surrounds the drain region.

2. The method of claim 1 , wherein forming the gate electrode stack comprises using a replacement gate process.

3. The method of claim 1 , wherein removing the portion of the epitaxial seed layer further comprises removing a portion between the three-dimensional channel region and the semiconductor substrate, and wherein the gate electrode stack surrounds the three-dimensional channel region.

4. A method of fabricating a semiconductor device, the method comprising:
forming a three-dimensional semiconductor structure on an epitaxial seed layer disposed above a semiconductor substrate, the epitaxial seed layer comprising a semiconductor material different from the three-dimensional semiconductor structure;
etching the three-dimensional semiconductor structure to provide a three-dimensional channel region and to expose portions of the epitaxial seed layer on either side of the three-dimensional channel region;
forming source and drain regions on either side of the three-dimensional channel region and on the epitaxial seed layer;
insulating the three-dimensional channel region and the source and drain regions from the semiconductor substrate by forming an insulating structure comprising one or more isolation pedestals, the insulating structure continuous with the semiconductor substrate;
removing a portion of the epitaxial seed layer;
forming a gate electrode stack at least partially surrounding the three-dimensional channel region; and
forming a pair of conducting contacts, one contact at least partially surrounding the source region, and another contact at least partially surrounding the drain region, wherein removing the portion of the epitaxial seed layer comprises removing a portion between the source and drain regions and the semiconductor substrate, and wherein the one contact surrounds the source region and the other contact surrounds the drain region.

5. The method of claim 4 , wherein forming the gate electrode stack comprises using a replacement gate process.

6. The method of claim 4 , wherein removing the portion of the epitaxial seed layer further comprises removing a portion between the three-dimensional channel region and the semiconductor substrate, and wherein the gate electrode stack surrounds the three-dimensional channel region.

Assignees

• Cappellani Annalisa
• Pethe Abhijit Jayant
• Ghani Tahir
• Gomez Harry
• Intel Corp

Inventors

• Cappellani Annalisa
• Pethe Abhijit Jayant
• Ghani Tahir
• Gomez Harry

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title