Program verify word line ramping delay for lower current consumption mode
US-2024395343-A1 · Nov 28, 2024 · US
US9484100B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9484100-B2 |
| Application number | US-201414299813-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 9, 2014 |
| Priority date | Jan 21, 2011 |
| Publication date | Nov 1, 2016 |
| Grant date | Nov 1, 2016 |
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Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.
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What is claimed is: 1. A method of operating a memory device, the method comprising: biasing a data line to a first potential, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells; biasing a source to a second potential substantially the same as the first potential, where the source is coupled to a second end of the first string and to a second end of the second string of memory cells; deactivatin…
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