Micro-benchmark analysis optimization for microprocessor designs

Patent metadata

Field	Value
Publication number	US-9483603-B2
Application number	US-201414293763-A
Country	US
Kind code	B2
Filing date	Jun 2, 2014
Priority date	Jun 2, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design.

First claim

What is claimed is:

1. A method for optimizing micro-benchmark analysis of a microprocessor design, the method comprising:
identifying a suite of micro-benchmarks, each corresponding to a micro-benchmark workload condition for the microprocessor design;
simulating, under each micro-benchmark workload condition, fine-grained operation of the microprocessor design to generate a set of micro-benchmark activity factors for the micro-benchmark workload condition, each micro-benchmark activity factor indicating an amount of activity monitored for a respective one of a plurality of sub-units of the microprocessor design under the micro-benchmark workload condition;
simulating coarse-grained operation of the microprocessor design to generate a set of commercial workload activity factors, each commercial workload activity factor indicating an amount of activity monitored for each respective one of the plurality of sub-units of the microprocessor design under a commercial workload condition;
calculating a set of weighting factors as a function of the micro-benchmark activity factors and the commercial workload activity factors to apply to the suite of micro-benchmarks to yield a weighted aggregate micro-benchmark workload condition that substantially approximates the commercial workload condition; and
fabricating a semiconductor integrated circuit according to a microprocessor design optimized to the yielded weighted aggregate micro-benchmark workload condition.

2. The method of claim 1 , wherein the calculating comprises minimizing a difference between the weighted aggregate micro-benchmark workload condition and the commercial workload.

3. The method of claim 1 , wherein the simulating fine-grained operation of the microprocessor design comprises performing a register transfer logic (RTL) level simulation of an architectural power model of the microprocessor design.

4. The method of claim 1 , further comprising:
setting a plurality of monitors in an architectural power model of the microprocessor design, each monitor configured to count occurrences of one or more of a predetermined set of key architectural behaviors in a respective one of the sub-units,
wherein each of the simulating fine-grained operation and the simulating coarse-grained operation comprises monitoring the amount of activity for each respective one of the plurality of sub-units of the microprocessor design according to the occurrences counted by the monitors.

5. The method of claim 4 , wherein each of the predetermined set of key architectural behaviors is associated with an amount of power consumed by the sub-unit when the key architectural behavior occurs, such that the set of micro-benchmark activity factors for each micro-benchmark workload condition indicates a power consumption of the microprocessor design under the micro-benchmark workload condition, and the set of commercial workload activity factors indicates a power consumption of the microprocessor design under the commercial workload condition.

6. The method of claim 4 , further comprising:
calculating a difference between the weighted aggregate micro-benchmark workload condition and the commercial workload by computing a root of sum square of elements of a vector defined by W*A−B, wherein:
A is a matrix defined by: sum{Wj*C.*AF(j), for j=1 . . . N};
B is a matrix defined by: C.*Target_AF;
each j corresponds to one of N micro-benchmarks in the suite of micro-benchmarks;
AF(j) is a vector corresponding to the set of micro-benchmark activity factors for the micro-benchmark workload condition associated with micro-benchmark j;
Target_AF is a vector corresponding to the set of commercial workload activity factors for the commercial workload condition;
C is a vector corresponding to a power consumption associated with each key architectural behavior; and
Wj is a vector corresponding to the set of weighting factors applied to the N micro-benchmarks.

7. The method of claim 6 , wherein the calculating the set of weighting factors comprises minimizing the difference between the weighted aggregate micro-benchmark workload condition and the commercial workload by applying a minimize function to:
∥ W*A−B∥^ 2,

subject to all elements of Wj being non-negative, wherein ∥ . . . ∥ computes a root of sum square of elements of a vector.

8. The method of claim 7 , wherein the minimize function comprises a convex optimization function.

9. The method of claim 7 , wherein applying the minimize function comprises:
computing a gradient of W (“grad(W)”) and an optimal W according to:
grad( w )∥ W*A−B∥^ 2= W ( A T A )−( A T B )=0,

so that the optimal W=(1/(A T A))*(A T B);
iteratively, while any element of the computed optimal W is less than zero:
identifying an element W as having a largest absolute negative value;
removing the micro-benchmark corresponding to the identified element from the N micro-benchmarks; and
re-computing the gradient of W and the optimal W; and
setting W to the optimal W when all elements of W are non-negative.

10. The method of claim 1 , wherein each micro-benchmark represents either a kernel in a common algorithm or a corner-case scenario.

Assignees

• Oracle Int Corp

Inventors

• Zhang Haowei
• Shen Xiaoying
• Turullols Sebastian

Classifications

• G06F17/11

  for solving equations {, e.g. nonlinear equations, general mathematical optimization problems (optimization specially adapted for a specific administrative, business or logistic context G06Q10/04)} · CPC title

• G06F2117/08

  HW-SW co-design, e.g. HW-SW partitioning · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title