Addressing multi-core advanced memory buffers

Patent metadata

Field	Value
Publication number	US-9483437-B2
Application number	US-86478107-A
Country	US
Kind code	B2
Filing date	Sep 28, 2007
Priority date	Sep 28, 2007
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

In some embodiments a method of addressing advanced memory buffers identifies whether a dual inline memory module includes more than one advanced memory buffer. If the dual inline memory module includes more than one advanced memory buffer, then each of the advanced memory buffers of the dual inline memory module is addressed separately, and an address is computed for a next dual inline memory module. Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
programmable logic to address a dual inline memory module; and
firmware to identify whether the dual inline memory module includes more than one advanced memory buffer, and if the dual inline memory module includes more than one advanced memory buffer, the firmware to program the programmable logic to address separately each of the advanced memory buffers of the dual inline memory module, and to compute an address for a next dual inline memory module and to program the programmable logic with the address for the next dual inline memory module.

2. The apparatus of claim 1 , the firmware further to identify whether the dual inline memory module includes one advanced memory buffer, and if the dual inline memory module includes one advanced memory buffer, the firmware to program the programmable logic to address the advanced memory buffer as a typical fully buffered dual inline memory module.

3. The apparatus of claim 1 , the programmable logic further to use the computed address for a second dual inline memory module, and the firmware further to identify whether the second dual inline memory module includes more than one advanced memory buffer, and if the second dual inline memory module includes more than one advanced memory buffer, then the firmware further to program the programmable logic to address separately each of the advanced memory buffers of the second dual inline memory module, and to compute an address for a next dual inline memory module and to program the programmable logic with the address for the next dual inline memory module.

4. The apparatus of claim 1 , the programmable logic further to identify for each dual inline memory module in a system whether that dual inline memory module includes more than one advanced memory buffer, and if that dual inline memory module includes more than one advanced memory buffer, the firmware to program the programmable logic to address separately each of the advanced memory buffers of that dual inline memory module, and to compute an address for a next dual inline memory module and to program the programmable logic with the address for the next dual inline memory module.

5. The apparatus of claim 1 , the firmware to program programmable logic in the dual inline memory module to address separately each of the advanced memory buffers of the dual inline memory module.

6. The apparatus of claim 1 , wherein the programmable logic is programmable logic on a motherboard and the firmware is firmware on a motherboard.

7. The apparatus of claim 1 , wherein the programmable logic is included in a memory controller hub.

8. A system comprising:
a dual inline memory module including at least one advanced memory buffer;
programmable logic to address the dual inline memory module; and
firmware to identify whether the dual inline memory module includes more than one advanced memory buffer, and if the dual inline memory module includes more than one advanced memory buffer, the firmware to program the programmable logic to address separately each of the advanced memory buffers of the dual inline memory module, and to compute an address for a next dual inline memory module and to program the programmable logic with the address for the next dual inline memory module.

9. The system of claim 8 , the firmware further to identify whether the dual inline memory module includes one advanced memory buffer, and if the dual inline memory module includes one advanced memory buffer, the firmware to program the programmable logic to address the advanced memory buffer as a typical fully buffered dual inline memory module.

10. The system of claim 8 , further comprising a second dual inline memory module, the programmable logic further to use the computed address for the second dual inline memory module, and the firmware further to identify whether the second dual inline memory module includes more than one advanced memory buffer, and if the second dual inline memory module includes more than one advanced memory buffer, then the firmware further to program the programmable logic to address separately each of the advanced memory buffers of the second dual inline memory module, and to compute an address for a next dual inline memory module and to program the programmable logic with the address for the next dual inline memory module.

11. The system of claim 8 , the programmable logic further to identify for each dual inline memory module in the system whether that dual inline memory module includes more than one advanced memory buffer, and if that dual inline memory module includes more than one advanced memory buffer, the firmware to program the programmable logic to address separately each of the advanced memory buffers of that dual inline memory module, and to compute an address for a next dual inline memory module and to program the programmable logic with the address for the next dual inline memory module.

12. The system of claim 8 , the firmware to program programmable logic in the dual inline memory module to address separately each of the advanced memory buffers of the dual inline memory module.

13. The system of claim 8 , wherein the programmable logic is programmable logic on a motherboard and the firmware is firmware on a motherboard.

14. The system of claim 8 , wherein the programmable logic is included in a memory controller hub.

Assignees

• Aditham Shiva
• Yang Steven C
• Intel Corp

Inventors

• Aditham Shiva
• Yang Steven C

Classifications

• G06F13/4243 Primary

  with synchronous protocol · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F13/4256

  using a clocked protocol · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title