Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources

Patent metadata

Field	Value
Publication number	US-9483266-B2
Application number	US-201313843020-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag. Some embodiments generate the test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction through a just-in-time compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.

First claim

What is claimed is:

1. A processor comprising:
a decode stage to decode a first instruction for execution, the first instruction specifying a first operand source data, a second operand source data, a third operand source data, and an operation type, wherein when said decode stage decodes the first instruction, it fuses the first instruction with a branch instruction for execution as a single fused micro-operation; and
one or more execution units, responsive to the decoded first instruction, to:
perform a first logical operation, according to the specified operation type, between data from the first and second operand sources, and
perform a second logical operation between the data from the third operand source and the result of the first logical operation to conditionally set a condition flag; and wherein

said one or more execution units, responsive to the single fused micro-operation, perform the first logical operation, test the result of the first logical operation against the third source data operand to conditionally set a zero flag, and conditionally branch if the zero flag gets set.

2. The processor of claim 1 , wherein performing the second logical operation comprises a logical AND operation and conditionally sets the zero flag.

3. The processor of claim 2 , wherein according to the specified operation type, a logical AND is performed between data from the first and second operands' source data.

4. The processor of claim 2 , wherein according to the specified operation type, a logical OR is performed between data from the first and second operands' source data.

5. A processor comprising:
a decode stage to decode:
a first instruction specifying a first source data operand, a second source data operand, and a third source data operand, and
a second instruction specifying a branch target;

said decode stage to fuse the first instruction with the second instruction for execution as a single fused micro-operation; and
one or more execution units, responsive to the single fused micro-operation, to:
perform a first logical operation between data from the first source data operand and the second source data operand,
perform a second logical operation to test the data from the third source data operand and the result of the first logical operation to set a zero condition flag, and
perform a conditional branch to the branch target if the zero condition flag gets set.

6. The processor of claim 5 , wherein performing the second logical operation comprises a logical TEST operation and conditionally sets the zero condition flag.

7. The processor of claim 6 , wherein according to the first instruction, a logical AND is performed between data from the first source data operand and the second source data operand.

8. The processor of claim 6 , wherein according to the first instruction, a logical OR is performed between data from the first source/destination data operand and the second source data operand.

9. A method comprising:
decoding a first instruction for execution, the first instruction specifying a first source data operand, a second source data operand, a third source data operand, and an operation type;
responsive to the decoded first instruction:
performing a first logical operation, according to the specified operation type, between data from the first and second source data operands, and
performing a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag;

fusing the first instruction with a branch instruction for execution as a single fused micro-operation; and
responsive to the single fused micro-operation, comprising:
performing the first logical operation,
testing the result of the first logical operation against the third source data operand to conditionally sets a zero flag, and
conditionally branching if the zero flag gets set.

10. The method of claim 9 , wherein performing the second logical operation comprises performing a logical AND operation and conditionally setting the zero flag.

11. The method of claim 10 , wherein according to the specified operation type, a logical AND is performed between data from the first and second source data operands.

12. The method of claim 10 , wherein according to the specified operation type, a logical OR is performed between data from the first and second source data operands.

13. A processing system comprising:
a memory; and
a plurality of processors including a first processor core and a second processor core each processor comprising:
a decode stage to decode a first instruction for execution, the first instruction specifying a first operand source data, a second operand source data, a third operand source data, and an operation type, wherein when said decode stage decodes the first instruction, it fuses the first instruction with a branch instruction for execution as a single fused micro-operation; and
one or more execution units, responsive to the decoded first instruction, to:
perform a first logical operation, according to the specified operation type, between data from the first and second operand sources, and
perform a second logical operation between the data from the third operand source and the result of the first logical operation to conditionally set a condition flag; and wherein

said one or more execution units, responsive to the single fused micro-operation, perform the first logical operation, test the result of the first logical operation against the third source data operand to conditionally set a zero flag, and conditionally branch if the zero flag gets set.

14. The processing system of claim 13 , wherein performing the second logical operation comprises a logical TEST operation and conditionally sets the zero flag.

15. The processing system of claim 14 , wherein according to the first instruction, a logical AND is performed between data from the first source/destination data operand and the second source data operand.

16. The processing system of claim 14 , wherein according to the first instruction, a logical OR is performed between data from the first source/destination data operand and the second source data operand.

Assignees

• Loktyukhin Maxim
• Valentine Robert
• Horn Julian C
• Charney Mark J
• Intel Corp

Inventors

• Loktyukhin Maxim
• Valentine Robert
• Horn Julian C
• Charney Mark J

Classifications

• G06F9/30094

  Condition code generation, e.g. Carry, Zero flag · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F9/30196

  using decoder, e.g. decoder per instruction set, adaptable or programmable decoders · CPC title

• G06F9/30029 Primary

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title